PCBA Cost and Complexity Design Factors You Should Know

PCBA designs evolve and become more complex, which is a persistent challenge for engineers and a major risk to the development process. Companies that neglect design complexity can end up slipping behind development schedules, incurring expenses, and missing market deadlines. 

Additionally, shortened design cycle times reduce available capacity to iterate from concept to first article prototypes, create customer samples, and ultimately build a production release amidst this increase in complexity. Engineers face pressure from both sides, having to do more with less time available. 

The purpose of this paper is to identify and explore common PCBA complexity factors, impacts, and possible mitigation techniques that can be undertaken before problems arise.

Effects of a Shortened Design Cycle

Many technical and business reasons contribute to the shrinking design cycle. Customer standards push technical boundaries to meet the changing specifications of demanding applications. As a result of persistent integration, design teams now compete to capture a more substantial share of fewer opportunities, accelerating their efforts to reach their goals. 

This sets up a mindset of doing things right the first time, which is not always possible. Although technical design tools have made the modern design process more comprehensive and efficient than a decade ago, electronic design is an iterative process regardless of how you try to approach it. 

If technological advances are not examined in depth before full production begins, issues and oversights may arise. Make certain technical manufacturing capabilities get planned, tested, and verified in accordance with a consistent validation process. 

Engineers validate prototypes during Engineering Validation Testing (EVT) to ensure the design architecture is functional. Design Validation Testing (DVT) measures performance against specifications and boundary conditions to prove that the design is ready for manufacturing. A Production Validation Test (PVT) is the first test to verify that a product can be manufactured in large quantities. 

With an intentional approach to validation, challenges can be solved earlier in the design flow, rather than becoming an unexpected late issue before the launch of the product. Your CM partner should have a design for manufacturing (DFM) plan template that helps your design team address manufacturing constraints early in the development process. An effective design plan identifies the challenges and how to overcome them. 

Bigger Challenges with Smaller Components

SMT (surface mount technology) challenges increase as components get smaller. Component counts have quadrupled in the last few years, while board sizes have remained constant. Designs have become more complex and dense. Several issues are associated with this. 

Solder bridging shorts are more likely to occur as pin pitches decrease. Components with smaller pin footprints require more attention to the pad design and solder paste application. The pad size needs to be compact enough to allow proper spacing that avoids solder bridging. It should, however, be large enough to accommodate the required solder paste and solder coverage to prevent a cold solder joint. 

Similarly, handling components becomes more challenging as subtle differences in absolute dimensions are now large relative to each other. 

The Most Common Design Issues 

Tombstoning 

Small two-pin passive components such as chip resistors and capacitors should lay horizontally flat on the PCB after assembly. Due to reflow effects on the component, the applied solder paste may not properly keep the device flat. It is possible that the component may raise up and settle vertically without properly completing an electrical path to both sides of the passive. This issue is called ‘Tombstoning’ since the vertical component visually resembles the look of a tombstone. 

Component placement depends on solder self-alignment after it is positioned by a pick-and-place machine. However, if the placement is initially skewed during mounting, then the component will not properly align to its pads.

 Furthermore, the application of solder paste on each pad works best when the solder melts evenly. A component may lift at one end if the whetting between the pads is uneven, causing an “open”. Preparing the SMT process for proper alignment and whetting will solve this tombstone issue during assembly. 

Copper Too Close to the PCB Edge 

When routing a trace, power, or ground plane near the side of a PCB, make sure to meet the design rules for the minimum copper distance to the PCB edge. Minimum spacing is required for a couple of reasons. If the design rules are not followed, the separation of the PCB array could result in metal fragments smearing at the edges. It could lead to unwanted shorts. 

Furthermore, impedance control can be more challenging near the edges of the PCB since the stack-up of materials can be at the limits of tolerance. Deficiencies in spacing could result in trace impedances outside specifications, leading to an unwanted transmission line effect. 

Inadequate Annular Ring 

A trace with a layer termination into a via uses an annular ring layout feature. This layout creates a via in the middle of a well-defined ring of trace signals. For this annular ring to be technically successful, it must allow complete electrical contact from the trace to the via. Several incorrect implementations have the potential to cause failure. 

Design the annular ring so that it provides an adequate ring area for drilling the via hole. The required dimensions are part of the layout rule for the PCB. Center the drill hole within the ring and don’t let it wander outside of a limited area. Otherwise, the via may only have limited partial electrical contact. Additionally, the via-to-via spacing to other nearby rings is critical to prevent shorts from continuous high-current over longer time periods due to conductive anodic filament formation. 

Acid Traps

Whenever traces are laid out with turns at an acute angle of 90 degrees or less, the acid used in PCB etching may get trapped in a small, confined space and not disperse evenly. To achieve the necessary PCB electrical features, photoresist material must be etched evenly. In the past, legacy etching techniques had this problem. Using outdated equipment or manufacturing without proper mitigation techniques could still pose a potential problem. 

Slivers 

There are several tools that can perform PCB array separation, with varying degrees of accuracy and effectiveness. Using a saw tool saves money, but excessive vibrations can cause slivers of PCB material and burs to protrude from the unfinished edges. Separation with a router tool allows more forgiving treatment of PCB edges, but still makes physical contact with them. Laser cutting produces the cleanest approach without any possibility of PCB or copper splinters, but may be prohibitive for lower-cost projects. Your DFM plan can guide the best approach. 

Via Problems 

Vias on PCBAs take many forms. Blind vias connect an outer layer with a single inner layer but do not reach the opposite outside layer. Buried vias are connections on the inner PCBA layers that are hidden on the outer layers. Since there is not a single drill hole that aligns a via through the complete board stack-up, alignment between layers needs to be precise. The Via in Pad, however, refers to a via within a solder pad that can be more challenging since the design rules are more complicated. 

Not all via combinations can be implemented, and advanced vias can increase manufacturing costs. Only use them if you have no alternatives. Via size is also a limiting factor in the selection of PCB technology. Manufacturing technology and complexity will dictate design rules. It is common for limitations to exist, such as: 

• Vias can only travel through an even number of layers 
• Vias cannot start or end at the top or bottom of a core 
• Vias may have minimum distance criteria from one another

In the case when a blind or buried via is required, your CM partner should work with you to provide a digital design tool that outlines the manufacturing rules for these cases. This tool should help with their design, limitation, and cost drivers. 

EMI Interference 

It is possible for the spatial routing of signals and the potential for antenna loops to impact the circuit layout. EMI interference within the PCB and externally can have an impact on performance and prevent EMI compliance certification by the FCC. Changing the layout, moving key components, and modifying the enclosure design can have a significant effect on EMI performance. Your CM partner can assist you in the complex design aspects of EMI interference. Additionally, they can assist in getting the final solution certified for EMI emissions by the FCC. 

Faster design cycles can be a competitive edge for those that have the capacity to execute. But they also involve new challenges to prepare the release of the design for successful manufacturing. Knowing the challenges in advance and preparing for them with your CM manufacturing partner help mitigate issues for a seamless transition from prototypes to large-volume production. 

By executing the project along the proper validation steps of EVT, DVT, and PVT, hidden challenges can be exposed early and solved during development before they become a problem during manufacturing. Work with an expert CM manufacturing partner to help guide your team through the transition of your project to production. 

MacroFab operates the world’s first digital electronics manufacturing platform for both low-volume prototype creation and high-scale production. The MacroFab platform enables customers to produce electronics products faster, more cost-effectively, and closer to their end-users via a broad North American factory network, all while leveraging MacroFab’s global supply chain and quality control capabilities. The company is headquartered in Houston, TX. Learn about the MacroFab Guarantee and securely upload your design to get a PCB assembly quote in minutes.