Single Sided PCB with Solder Mask and Surface Mount Components

In this comprehensive guide, we will explore the design, manufacturing process, advantages, and limitations of single sided PCBs, helping you understand their critical role in modern electronics.

Single Sided PCB: A Comprehensive Guide

As computer chips continue to get smaller and more complex, the ultrathin metallic wires that carry electrical signals within these chips have become a weak link. Standard metal wires get worse at conducting electricity as they get thinner, ultimately limiting the size, efficiency, and performance of nanoscale electronics.In a <a href="https://www.science.org/doi/10.1126/science.adq7096" data-extlink="">paper</a> published Jan. 3 in Science, Stanford researchers show that niobium phosphide can conduct electricity better than copper in films that are only a few atoms thick. Moreover, these films can be created and deposited at sufficiently low temperatures to be compatible with modern computer chip fabrication. Their work could help make future electronics more powerful and more energy efficient.“We are breaking a fundamental bottleneck of traditional materials like copper,” said<a href="https://profiles.stanford.edu/asir" data-extlink="">&nbsp;Asir Intisar Khan</a>, who received his doctorate from Stanford and is now a visiting postdoctoral scholar and first author on the paper. “Our niobium phosphide conductors show that it’s possible to send faster, more efficient signals through ultrathin wires. This could improve the energy efficiency of future chips, and even small gains add up when many chips are used, such as in the massive data centers that store and process information today.”<h2>A new class of conductors</h2>Niobium phosphide is what researchers call a topological semimetal, which means that the whole material can conduct electricity, but its outer surfaces are more conductive than the middle. As a film of niobium phosphide gets thinner, the middle region shrinks but its surfaces stay the same, allowing the surfaces to contribute a greater share to the flow of electricity and the material as a whole to become a better conductor. Traditional metals like copper, on the other hand, become worse at conducting electricity once they are thinner than about 50 nanometers.The researchers found that niobium phosphide became a better conductor than copper at film thicknesses below 5 nanometers, even when operating at room temperature. At this size, copper wires struggle to keep up with rapid-fire electrical signals and lose a lot more energy to heat.“Really high-density electronics need very thin metal connections, and if those metals are not conducting well, they are losing a lot of power and energy,” said<a href="https://profiles.stanford.edu/epop" data-extlink="">&nbsp;Eric Pop</a>, the Pease-Ye Professor in the School of Engineering, a professor of electrical engineering, and senior author on the paper. “Better materials could help us spend less energy in small wires and more energy actually doing computation.”<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1736817677357-nbpconductors_schematic_1500_1_0.jpg.webp" style="width: 100%px;" class="fr-fic fr-dib">A film a few atoms thick of non-crystalline niobium phosphide conducts better through the surface to make the material, as a whole, a better conductor. | Il-Kwon Oh / Asir KhanMany researchers have been working to find better conductors for nanoscale electronics, but so far the best candidates have had extremely precise crystalline structures, which need to be formed at very high temperatures. The niobium phosphide films made by Khan and his colleagues are the first examples of non-crystalline materials that become better conductors as they get thinner.“It has been thought that if we want to leverage these topological surfaces, we need nice single-crystalline films that are really hard to deposit,” said Akash Ramdas, a doctoral student at Stanford and co-author on the paper. “Now we have another class of materials – these topological semimetals – that could potentially act as a way to reduce energy usage in electronics.”Because the niobium phosphide films don’t need to be single crystals, they can be created at lower temperatures. The researchers deposited the films at 400 degrees Celsius, a temperature that is low enough to avoid damaging or destroying existing silicon computer chips.“If you have to make perfect crystalline wires, that’s not going to work for nanoelectronics,” said<a href="https://profiles.stanford.edu/yuri-suzuki" data-extlink="">&nbsp;Yuri Suzuki</a>, the Stanley G. Wojcicki Professor in the&nbsp;<a href="https://humsci.stanford.edu/" data-extlink="">School of Humanities and Sciences</a>, a professor of applied physics and co-author on the paper. “But if you can make them amorphous or slightly disordered and they still give you the properties you need, that opens the door to potential real-world applications.”<h2>Enabling future nanoelectronics</h2>Although niobium phosphide films are a promising start, Pop and his colleagues don’t expect them to suddenly replace copper in all computer chips – copper is still a better conductor in thicker films and wires. But niobium phosphide could be used for the very thinnest connections, and it paves the way for research into conductors made of other topological semimetals. The researchers are already looking into similar materials to see if they can improve niobium phosphide’s performance.“For this class of materials to be adopted in future electronics, we need them to be even better conductors,” said Xiangjin Wu, a doctoral student at Stanford and co-author on the paper. “To that end, we are exploring alternative topological semimetals.”Pop and his team are also working on turning their niobium phosphide films into narrow wires for additional testing. They want to determine how reliable and effective the material could be in real-world applications.“We’ve taken some really cool physics and ported it into the applied electronics world,” Pop said. “This kind of breakthrough in non-crystalline materials could help address power and energy challenges in both current and future electronics.”<hr>Pop is also professor, by courtesy, of materials science and engineering in the School of Engineering and of applied physics in the School of Humanities and Sciences. He is the faculty co-director of<a href="https://systemx.stanford.edu/" data-extlink="">&nbsp;Stanford SystemX</a>&nbsp;and a senior fellow of the<a href="https://energy.stanford.edu/" data-extlink="">&nbsp;Precourt Institute for Energy</a>.Suzuki is also professor, by courtesy, of materials science and engineering in the School of Engineering and is the director of<a href="https://snsf.stanford.edu/" data-extlink="">&nbsp;Stanford Nano Shared Facilities</a>&nbsp;and a member of<a href="http://biox.stanford.edu/" data-extlink="">&nbsp;Stanford Bio-X</a>.Additional Stanford co-authors of this research are Krishna Saraswat, the Ricky/Nielsen Professor in the School of Engineering; Felipe H. da Jornada, assistant professor of materials science and engineering; and graduate student Emily Lindgren.Other co-authors of this work are from Ajou University, Korea Electronics Technology Institute, and IBM T.J. Watson Research Center.

A patterned chip with Hall bar devices of ultrathin niobium phosphide film. | Asir Khan / Eric Pop

Researchers at Stanford Engineering have developed an ultrathin material that conducts electricity better than copper and could enable more energy-efficient nanoelectronics.

A new ultrathin conductor for nanoelectronics

Now, researchers at Princeton Engineering and the Indian Institute of Technology have harnessed artificial intelligence to take a key step toward slashing the time and cost of designing new wireless chips and discovering new functionalities to meet expanding demands for better wireless speed and performance. In an <a href="https://www.nature.com/articles/s41467-024-54178-1">article</a> published Dec. 30 in Nature Communications, the researchers describe their methodology, in which an AI creates complicated electromagnetic structures and associated circuits in microchips based on the design parameters. What used to take weeks of highly skilled work can now be accomplished in hours.What is more, the AI behind the new system has produced strange new designs featuring unusual patterns of circuitry. <a href="https://engineering.princeton.edu/faculty/kaushik-sengupta">Kaushik Sengupta</a>, the lead researcher, said the designs were unintuitive and unlikely to be developed by a human mind. But they frequently offer marked improvements over even the best standard chips.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1736384954679-16x9-SenguptaLab_111224_0024-1536x864.jpg" style="width: 100%px;" class="fr-fic fr-dib">Professor Kaushik Sengupta, left, and first author Emir Ali Karahan, a gradate student in electrical and computer engineering. Photos by Tori Repp/Fotobuddy“We are coming up with structures that are complex and look random shaped and when connected with circuits, they create previously unachievable performance. Humans cannot really understand them, but they can work better,” said Sengupta, a professor of <a href="https://ece.princeton.edu/">electrical and computer engineering</a> and co-director of <a href="https://nextg.princeton.edu/">NextG</a>, Princeton’s industry partnership program to develop next-generation communications.These circuits can be engineered toward more energy efficient operation or to make them operable across an enormous frequency range that is not currently possible. Furthermore, the method synthesizes inherently complex structures in minutes, while conventional algorithms may take weeks. In some cases, the new methodology can create structures that are impossible to synthesize with current techniques.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1736384973762-16X9-SenguptaLab_111224_0020-1536x864.jpg" style="width: 100%px;" class="fr-fic fr-dib">An enlarged image of the chip’s circuitry in Sengupta’s lab at Princeton.Uday Khankhoje, a co-author and associate professor of electrical engineering at IIT Madras, said the new technique not only delivers efficiency but promises to unlock new approaches to design challenges that have been beyond the capability of engineers.“This work presents a compelling vision of the future,” he said. “AI powers not just the acceleration of time-consuming electromagnetic simulations, but also enables exploration into a hitherto&nbsp;unexplored design space and delivers stunning high-performance devices that run counter to the usual rules of thumb and human intuition.”Wireless chips are a combination of standard electronic circuits like those in computer chips and electromagnetic structures including antennas, resonators, signal splitters, combiners and others. These combinations of elements are put together in every circuit block, carefully handcrafted and co-designed to operate optimally. &nbsp;This method is then scaled to other circuits, sub-systems and systems, making the design process extremely complex and time consuming, particularly for modern, high-performance chips behind applications like wireless communication, autonomous driving, radar and gesture recognition.“Classical designs, carefully, put these circuits and electromagnetic elements together, piece by piece, so that the signal flows in the way we want it to flow in the chip. By changing those structures, we incorporate new properties,” Sengupta said. “Before, we had a finite way of doing this, but now the options are much larger.”<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1736384992892-sengupta-lap-chip-1536x864.jpg" style="width: 100%px;" class="fr-fic fr-dib">An enlarged image of the chip’s circuitry shows unusual patterns.It can be hard to comprehend the vastness of a wireless chip’s design space. The circuitry in an advanced chip is so small, and the geometry so detailed, that the number of possible configurations for a chip exceeds the number of atoms in the universe, Sengupta said. There is no way for a person to understand that level of complexity, so human designers don’t try. They build chips from the bottom up, adding components as needed and adjusting the design as they build.The AI approaches the challenge from a different perspective, Sengupta said. It views the chip as a single artifact. This can lead to strange, but effective arrangements. He said humans play a critical role in the AI system, in part because that AI can make faulty arrangements as well as efficient ones. It is possible for AI to hallucinate elements that don’t work, at least for now. This requires some level of human oversight.“There are pitfalls that still require human designers to correct,” Sengupta said. “The point is not to replace human designers with tools. The point is to enhance productivity with new tools. The human mind is best utilized to create or invent new things, and the more mundane, utilitarian work can be offloaded to these tools.”The researchers have used AI to discover and design complex electromagnetic structures that are co-designed with circuits to create broadband amplifiers. Sengupta said future research will involve linking multiple structures and designing entire wireless chips with the AI system.“Now that this has shown promise, there is a larger effort to think about more complicated systems and designs,” he said. “This is just the tip of the iceberg in terms of what the future holds for the field.”<hr>The article, “<a href="https://www.nature.com/articles/s41467-024-54178-1">Deep-learning Enabled Generalized Inverse Design of Multi-Port Radio-frequency and Sub-Terahertz Passives and Integrated Circuits</a>,” was published Dec. 30, 2024, in the journal Nature Communications. Besides Sengupta, authors included Emir Ali Karahan, the lead author and a graduate student at Princeton; Zheng Liu, Zijian Shao and Jonathan Zhou of Princeton; and Aggraj Gupta and Uday Khankhoje of the Indian Institute of Technology Madras. Support for the research was provided in part by the Air Force Office of Scientific Research, the Office of Naval Research, Princeton Research Computing and the M. S. Chadha Center for Global India at Princeton University.

The AI design features unusual, and efficient, circuity patterns. Photo by Emir Ali Karahan, Princeton University

Specialized microchips that manage signals at the cutting edge of wireless technology are astounding works of miniaturization and engineering. They’re also difficult and expensive to design.

AI slashes cost and time for chip design, but that is not all

Explore how PCB drilling forms the backbone of modern electronics by enabling seamless circuit connectivity and ensuring robust device performance. Learn practical insights and expert tips to optimize your manufacturing process.

PCB Drilling: Precision Techniques for Modern Electronics

Monitoring electrical signals in biological systems helps scientists understand how cells communicate, which can aid in the diagnosis and treatment of conditions like arrhythmia and Alzheimer’s.But devices that record electrical signals in cell cultures and other liquid environments often use wires to connect each electrode on the device to its respective amplifier. Because only so many wires can be connected to the device, this restricts the number of recording sites, limiting the information that can be collected from cells.MIT researchers have now developed a biosensing technique that eliminates the need for wires. Instead, tiny, wireless antennas use light to detect minute electrical signals.Small electrical changes in the surrounding liquid environment alter how the antennas scatter the light. Using an array of tiny antennas, each of which is one-hundredth the width of a human hair, the researchers could measure electrical signals exchanged between cells, with extreme spatial resolution.The devices, which are durable enough to continuously record signals for more than 10 hours, could help biologists understand how cells communicate in response to changes in their environment. In the long run, such scientific insights could pave the way for advancements in diagnosis, spur the development of targeted treatments, and enable more precision in the evaluation of new therapies.“Being able to record the electrical activity of cells with high throughput and high resolution remains a real problem. We need to try some innovative ideas and alternate approaches,” says Benoît Desbiolles, a former postdoc in the MIT Media Lab and lead author of <a href="https://doi.org/10.1126/sciadv.adr8380" target="_blank">a paper on the devices</a>.He is joined on the paper by Jad Hanna, a visiting student in the Media Lab; former visiting student Raphael Ausilio; former postdoc Marta J. I. Airaghi Leccardi; Yang Yu, a scientist at Raith America, Inc.; and senior author Deblina Sarkar, the AT&amp;T Career Development Assistant Professor in the Media Lab and MIT Center for Neurobiological Engineering and head of the Nano-Cybernetic Biotrek Lab. The research appears today in Science Advances.“Bioelectricity is fundamental to the functioning of cells and different life processes. However, recording such electrical signals precisely has been challenging,” says Sarkar. “The organic electro-scattering antennas (OCEANs) we developed enable recording of electrical signals wirelessly with micrometer spatial resolution from thousands of recording sites simultaneously. This can create unprecedented opportunities for understanding fundamental biology and altered signaling in diseased states as well as for screening the effect of different therapeutics to enable novel treatments.”<h2>Biosensing with light</h2>The researchers set out to design a biosensing device that didn’t need wires or amplifiers. Such a device would be easier to use for biologists who may not be familiar with electronic instruments.“We wondered if we could make a device that converts the electrical signals to light and then use an optical microscope, the kind that is available in every biology lab, to probe these signals,” Desbiolles says.Initially, they used a special polymer called PEDOT:PSS to design nanoscale transducers that incorporated tiny pieces of gold filament. Gold nanoparticles were supposed to scatter the light — a process that would be induced and modulated by the polymer. But the results weren’t matching up with their theoretical model.The researchers tried removing the gold and, surprisingly, the results matched the model much more closely.“It turns out we weren’t measuring signals from the gold, but from the polymer itself. This was a very surprising but exciting result. We built on that finding to develop organic electro-scattering antennas,” he says.The&nbsp;organic electro-scattering antennas,&nbsp;or OCEANs, are composed of&nbsp;PEDOT:PSS. This polymer attracts or repulses positive ions from the surrounding liquid environment when there is electrical activity nearby. This modifies its chemical configuration and electronic structure, altering an optical property known as its refractive index, which changes how it scatters light.When researchers shine light onto the antenna, the intensity of the light changes in proportion to the electrical signal present in the liquid.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1735259967015-ezgif-4-326702faf8.gif" style="width: 100%px;" class="fr-fic fr-dib">The brightness of light scattered by the tiny antennas the researchers developed, called OCEANs, changes in response to changing electrical signals in the liquid environment that surrounds them, as shown here. By capturing and measuring the light with an optical microscope, researchers could decode the intricate signals used for cellular communication. Credit: Courtesy of the researchersWith thousands or even millions of tiny antennas in an array, each only 1 micrometer wide, the researchers can capture the scattered light with an optical microscope and measure electrical signals from cells with high resolution. Because each antenna is an independent sensor, the researchers do not need to pool the contribution of multiple antennas to monitor electrical signals, which is why OCEANs can detect signals with micrometer resolution.Intended for in vitro&nbsp;studies, OCEAN arrays are designed to have cells cultured directly on top of them and put under an optical microscope for analysis.<h2>“Growing” antennas on a chip</h2>Key to the devices is the precision with which the researchers can fabricate arrays in the MIT.nano facilities.They start with a glass substrate and deposit layers of conductive then insulating material on top, each of which is optically transparent. Then they use a focused ion beam to cut hundreds of nanoscale holes into the top layers of the device. This special type of focused ion beam enables high-throughput nanofabrication.“This instrument is basically like a pen where you can etch anything with a 10-nanometer resolution,” he says.They submerge the chip in a solution that contains the precursor building blocks for the polymer. By applying an electric current to the solution, that precursor material is attracted into the tiny holes on the chip, and mushroom-shaped antennas “grow” from the bottom up.The entire fabrication process is relatively fast, and the researchers could use this technique to make a chip with millions of antennas.“This technique could be easily adapted so it is fully scalable. The limiting factor is how many antennas we can image at the same time,” he says.The researchers optimized the dimensions of the antennas and adjusted parameters, which enabled them to achieve high enough sensitivity to monitor signals with voltages as low as 2.5 millivolts in simulated experiments. Signals sent by neurons for communication are usually around 100 millivolts.“Because we took the time to really dig in and understand the theoretical model behind this process, we can maximize the sensitivity of the antennas,” he says.OCEANs also responded to changing signals in only a few milliseconds, enabling them to record electrical signals with fast kinetics. Moving forward, the researchers want to test the devices with real cell cultures. They also want to reshape the antennas so they can penetrate cell membranes, enabling more precise signal detection.In addition, they want to study how OCEANs could be integrated into nanophotonic devices, which manipulate light at the nanoscale for next-generation sensors and optical devices.This research is funded, in part, by the U.S. National Institutes of Health and the Swiss National Science Foundation. Research reported in this press release was supported by the National Heart, Lung, and Blood Institute (NHLBI) of the National Institutes of Health and does not necessarily represent the official views of the NIH.

To improve biosensing techniques that can aid in diagnosis and treatment, MIT researchers developed tiny, wireless antennas that use light to detect minute electrical signals in liquid environments, which are shown in this rendering. Credit: Marta Airaghi and Benoit Desbiolles

As part of a high-resolution biosensing device without wires, the antennas could help researchers decode intricate electrical signals sent by cells.

Tiny, wireless antennas use light to monitor cellular communication

The electronics industry is approaching a limit to the number of transistors that can be packed onto the surface of a computer chip. So, chip manufacturers are looking to build up rather than out.Instead of squeezing ever-smaller transistors onto a single surface, the industry is aiming to stack multiple surfaces of transistors and semiconducting elements — akin to turning a ranch house into a high-rise. Such multilayered chips could handle exponentially more data and carry out many more complex functions than today’s electronics.A significant hurdle, however, is the platform on which chips are built. Today, bulky silicon wafers serve as the main scaffold on which high-quality, single-crystalline semiconducting elements are grown. Any stackable chip would have to include thick silicon “flooring” as part of each layer, slowing down any communication between functional semiconducting layers.Now, MIT engineers have found a way around this hurdle, with a multilayered chip design that doesn’t require any silicon wafer substrates and works at temperatures low enough to preserve the underlying layer’s circuitry.In a study <a href="https://www.nature.com/articles/s41586-024-08236-9" target="_blank">appearing today in the journal Nature</a>, the team reports using the new method to fabricate a multilayered chip with alternating layers of high-quality semiconducting material grown directly on top of each other.The method enables engineers to build high-performance transistors and memory and logic elements on any random crystalline surface — not just on the bulky crystal scaffold of silicon wafers. Without these thick silicon substrates, multiple semiconducting layers can be in more direct contact, leading to better and faster communication and computation between layers, the researchers say.The researchers envision that the method could be used to build AI hardware, in the form of stacked chips for laptops or wearable devices, that would be as fast and powerful as today’s supercomputers and could store huge amounts of data on par with physical data centers.“This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” says study author Jeehwan Kim, associate professor of mechanical engineering at MIT. “This could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.”The study’s MIT co-authors include first author Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, along with collaborators from Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas at Dallas.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1735004985635-MIT-Direct-Stack-02-press.jpg" style="width: 100%px;" class="fr-fic fr-dib">“This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” says Jeehwan Kim. Credit: Cube 3D Graphic<h2>Seed pockets</h2>In 2023, Kim’s group <a href="https://news.mit.edu/2023/2d-atom-thin-industrial-silicon-wafers-0118" target="_blank">reported</a> that they developed a method to grow high-quality semiconducting materials on amorphous surfaces, similar to the diverse topography of semiconducting circuitry on finished chips. The material that they grew was a type of 2D material known as transition-metal dichalcogenides, or TMDs, considered a promising successor to silicon for fabricating smaller, high-performance transistors. Such 2D materials can maintain their semiconducting properties even at scales as small as a single atom, whereas silicon’s performance sharply degrades.In their previous work, the team grew TMDs on silicon wafers with amorphous coatings, as well as over existing TMDs. To encourage atoms to arrange themselves into high-quality single-crystalline form, rather than in random, polycrystalline disorder, Kim and his colleagues first covered a silicon wafer in a very thin film, or “mask” of silicon dioxide, which they patterned with tiny openings, or pockets. They then flowed a gas of atoms over the mask and found that atoms settled into the pockets as “seeds.” The pockets confined the seeds to grow in regular, single-crystalline patterns.But at the time, the method only worked at around 900 degrees Celsius.“You have to grow this single-crystalline material below 400 Celsius, otherwise the underlying circuitry is completely cooked and ruined,” Kim says. “So, our homework was, we had to do a similar technique at temperatures lower than 400 Celsius. If we could do that, the impact would be substantial.”<h2>Building up</h2>In their new work, Kim and his colleagues looked to fine-tune their method in order to grow single-crystalline 2D materials at temperatures low enough to preserve any underlying circuitry. They found a surprisingly simple solution in metallurgy — the science and craft of metal production. When metallurgists pour molten metal into a mold, the liquid slowly “nucleates,” or forms grains that grow and merge into a regularly patterned crystal that hardens into solid form. Metallurgists have found that this nucleation occurs most readily at the edges of a mold into which liquid metal is poured.“It’s known that nucleating at the edges requires less energy — and heat,” Kim says. “So we borrowed this concept from metallurgy to utilize for future AI hardware.”The team looked to grow single-crystalline TMDs on a silicon wafer that already has been fabricated with transistor circuitry. They first covered the circuitry with a mask of silicon dioxide, just as in their previous work. They then deposited “seeds” of TMD at the edges of each of the mask’s pockets and found that these edge seeds grew into single-crystalline material at temperatures as low as 380 degrees Celsius, compared to seeds that started growing in the center, away from the edges of each pocket, which required higher temperatures to form single-crystalline material.Going a step further, the researchers used the new method to fabricate a multilayered chip with alternating layers of two different TMDs — molybdenum disulfide, a promising material candidate for fabricating n-type transistors; and&nbsp;tungsten diselenide, a material that has potential for being made into p-type transistors. Both p- and n-type transistors are the electronic building blocks for carrying out any logic operation. The team was able to grow both materials in single-crystalline form, directly on top of each other, without requiring any intermediate silicon wafers. Kim says the method will effectively double the density of a chip’s semiconducting elements, and particularly, metal-oxide semiconductor (CMOS), which is a basic building block of a modern logic circuitry.“A product realized by our technique is not only a 3D logic chip but also 3D memory and their combinations,” Kim says. “With our growth-based monolithic 3D method, you could grow tens to hundreds of logic and memory layers, right on top of each other, and they would be able to communicate very well.”“Conventional 3D chips have been fabricated with silicon wafers in-between, by drilling holes through the wafer — a process which limits the number of stacked layers, vertical alignment resolution, and yields,” first author Kiseok Kim adds. “Our growth-based method addresses all of those issues at once.”&nbsp;To commercialize their stackable chip design further, Kim has recently spun off a company, FS2 (Future Semiconductor 2D materials).“We so far show a concept at a small-scale device arrays,” he says. “The next step is scaling up to show professional AI chip operation.”This research is supported, in part, by Samsung Advanced Institute of Technology and the U.S. Air Force Office of Scientific Research.&nbsp;

MIT engineers have developed a method to seamlessly stack electronic layers to create faster, denser, more powerful computer chips. The team deposits semiconducting particles (in pink) as triangles within confined squares, to create high-quality electronic elements, directly atop other semiconducting layers (shown in layers of purple, blue, and green). Credit: Cube 3D Graphic

An electronic stacking technique could exponentially increase the number of transistors on chips, enabling more efficient AI hardware.

Engineers grow "high-rise" 3D chips

Have you ever wondered how your car’s engine manages to stay efficient or how your smartphone prevents overheating? Behind these feats lies the NTC thermistor. This article will explore NTC Thermistor’s working principles, characteristics, applications, and challenges.

What Is An NTC Thermistor: A Guide to This Temperature-Sensitive Resistor

GPUs excel in parallel processing for graphics and AI training with scalability, while NPUs focus on low-latency AI inference on edge devices, enhancing privacy by processing data locally. Together, they complement each other in addressing different stages of AI workloads efficiently.

NPU vs GPU: Understanding the Key Differences and Use Cases

Diode Symbols: A Comprehensive Guide to Understanding Circuit Diagrams

Ever wondered how batteries power your gadgets or how metals are refined to their purest forms? The answers lie in the interplay of cathodes and anodes, two simple yet critical components in electrochemistry. This article will delve into their workings, applications, and challenges.


Cathode Anode: The Basics and Applications

<h3 id="isPasted">introducing Electroforming&nbsp;</h3><a href="https://www.vecoprecision.com/electroforming/" rel="noopener" target="_blank">Electroforming&nbsp;</a>is a metal&nbsp;fabrication process&nbsp;in which metal is electrochemically deposited onto a mold,&nbsp;also called&nbsp;a mandrel. The metal is deposited layer by layer, enabling the production of highly accurate and complicated&nbsp;components&nbsp;that would be difficult or impossible to manufacture using traditional methods such as stamping or machining. In contrast to stamping or machining, which are constrained by the intricacy of the part design and can result in substantial material waste,&nbsp;Electroforming may produce extremely complicated patterns with&nbsp;minimal waste.<h3>Electroforming for Electronics: what makes it the optical choice</h3>Electroforming stands out for its remarkable dimensional accuracy. Contrary to conventional manufacturing techniques, Electroforming may reach tolerances as low as ±1μm, &nbsp;making it perfect for creating electronic components, especially for uses where accuracy and size are crucial, such as wearable technology, drones, and consumer electronics. With Electroforming, tight tolerances, miniaturized size and volume, and consistent quality can be achieved to enhance functionality.&nbsp;The Electroforming technology also excels in creating complex, multi-layer geometries that would be impossible or too expensive to produce through traditional manufacturing techniques. With <a href="https://insights.vecoprecision.com/electroforming-can-be-more-than-2d-meet-multi-layer-electroforming" rel="noopener" target="_blank">multi-layer Electroforming</a>, &nbsp;3D or 2.5D structures can be achieved, including complex structures, undercuts, and internal features. This opens up the window for high-precision components that also demand delicate structures, particularly valuable in creating sophisticated electronic components that require complex internal geometries.<img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1733710771099-1733710771099.png" width="740" height="523" alt=" complex, multi-layer structure made by Electroforming" srcset="https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg?width=370&amp;height=262&amp;name=Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg 370w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg?width=740&amp;height=523&amp;name=Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg 740w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg?width=1110&amp;height=785&amp;name=Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg 1110w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg?width=1480&amp;height=1046&amp;name=Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg 1480w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg?width=1850&amp;height=1308&amp;name=Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg 1850w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg?width=2220&amp;height=1569&amp;name=Complex%20multi-layer%20structure%20created%20by%20Electroforming.jpg 2220w" sizes="(max-width: 740px) 100vw, 740px" class="fr-fic fr-dii">&nbsp;complex, multi-layer structure made by ElectroformingAnother significant advantage of Electroforming technology is its high degree of customizability, particularly when combined with Laser Direct Imaging (LDI) technology. The LDI system directly translates digital designs into physical patterns on the substrate, which means no need for physical photo masks anymore. This enables engineers to easily realize complex designs and make rapid design iterations without additional costs of tooling or mask-making. Complex geometric patterns, fine details, and sophisticated features can be incorporated into the design efficiently and cost-effectively. This level of design flexibility proves invaluable in both prototyping and volume production scenarios, empowering engineers to pursue advanced component designs to make next-gen breakthroughs. ➡️ <a href="https://insights.vecoprecision.com/advanced-lithographic-electroforming-what-makes-veco-the-industry-leader-of-precision-engineering" rel="noopener" target="_blank">learn more about LDI technology and how it empowers Advanced Lithographic Electroforming</a>Furthermore, the Electroformed components exhibit superior material properties due to their fine-grain structure. This results in excellent mechanical strength, superior electrical conductivity, and an optimal strength-to-weight ratio – all critical factors in electronic device manufacturing. <a href="https://www.vecoprecision.com/electroforming/materials-used-in-electroforming/" rel="noopener" target="_blank">A</a><a href="https://www.vecoprecision.com/electroforming/materials-used-in-electroforming/" rel="noopener" target="_blank">&nbsp;variety of metals (learn more about materials used in Electroforming in details here)</a>, including copper, nickel, gold, platinum, and silver, can be used with Electroforming technology, offering flexibility in terms of electrical and thermal conductivity, corrosion resistance, and mechanical strength. &nbsp;<h3>applications of Electroforming in Electronics</h3>The electronics sector, where accuracy and compactness are essential, is already benefiting greatly from Electroforming. Among the applications are: <img src="https://s3-us-west-1.amazonaws.com/wevolver-project-images/froala%2F1733710771337-1733710771337.png" width="1024" height="768" alt="electronics img" srcset="https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/electronics%20img.jpeg?width=512&amp;height=384&amp;name=electronics%20img.jpeg 512w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/electronics%20img.jpeg?width=1024&amp;height=768&amp;name=electronics%20img.jpeg 1024w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/electronics%20img.jpeg?width=1536&amp;height=1152&amp;name=electronics%20img.jpeg 1536w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/electronics%20img.jpeg?width=2048&amp;height=1536&amp;name=electronics%20img.jpeg 2048w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/electronics%20img.jpeg?width=2560&amp;height=1920&amp;name=electronics%20img.jpeg 2560w, https://insights.vecoprecision.com/hs-fs/hubfs/Veco/Images/electronics%20img.jpeg?width=3072&amp;height=2304&amp;name=electronics%20img.jpeg 3072w" sizes="(max-width: 1024px) 100vw, 1024px" class="fr-fic fr-dii"><ul><li>personal care: Personal care: Ultra-thin, sharp shaver foils for high-end electric shavers are made via Electroforming, and electroplating is an option for improved cutting performance and longevity.</li><li>inkjet printing:&nbsp;With Electroforming, high-quality inkjet nozzle plates with unparalleled jetting performance, superior chemical and mechanical stability can be achieved, enabling optimal printing performance.</li><li>hearing&nbsp;aid&nbsp;components: Electroforming is the choice of technique in the production of high precision and lightweight hearing aid components, which fit within the confined spaces of modern hearing aids.</li><li>nebulizer&nbsp;components: In medical electronics, electroformed components such as nebulizer plates play a vital role of controlling airflow and particle size, ensuring the effective delivery of medication.</li><li>drones: Electroforming is used to create lightweight, high strength, high precision components such as battery foils, structural elements, micro sensor components, helping enhance flight efficiency and longevity.</li></ul>➡️ <a href="https://www.vecoprecision.com/products/" rel="noopener" target="_blank">learn more about applications of Electroforming&nbsp;</a><h3>looking ahead: smaller, smarter, and greener</h3>As the electronics industry continues the trend toward miniaturization, Electroforming's capabilities become increasingly suitable for the production of next-gen electronics components. The technology is particularly well-suited for the emerging field of wearable electronics, where components must be not only small and precise but also flexible and biocompatible. Electroforming enables the creation of ultra-thin flexible circuits, integrated antenna structures, and miniature sensor housings that can be comfortably worn on the body.The capacity of Electroforming technology to produce intricate structures with high precision at the microscale also makes it perfect for innovative smart applications. For instance, it is also the best option for producing cutting-edge applications like components for quantum computing, micro-battery technology, and 3D semiconductor packaging.In addition, the capability to create high-quality <a href="https://www.vecoprecision.com/products/" rel="noopener" target="_blank">precision engineered components&nbsp;</a>with minimal waste and 100% green energy represents a big step toward more sustainable electronics manufacturing. As industries worldwide focus on reducing environmental impact, Electroforming's highly efficient material usage and lower energy demand make it increasingly meaningful. In addition, Veco has made the transition to 100% renewable energy since 2021, obtaining 50% of its energy from solar and 50% from wind sources. This commitment to sustainability extends beyond products to the entire operational philosophy, empowering our customers and pushing boundaries of innovations in a sustainable way.

This blog looks into the Electroforming technology, its technical advantages, why it is the optimal choice for the electronics industry, and its potential to transform the future of the electronics industry.

Electroforming for Electronics: advancing precision manufacturing for smaller, smarter, and greener devices

Have you considered how modern communication systems, like GSM networks, satellite communications, and broadcasting, manage multiple signals with precision? RF diplexers and duplexers make seamless signal sharing and optimal performance possible. Let’s explore the technology in this article.

Duplexer vs Diplexer: A Technical Guide to RF Signal Management Components

<section id="isPasted">The combination of light-based and electronic components on a single computer chip would have many benefits for our computing needs. Chips would be faster and consume less energy when using light. However, the problem with current silicon-based technologies is that they cannot emit light. TU/e full professor Erik Bakkers has big plans to change that, though. Along with colleagues at TU Munich and the University of Twente, the research team has just been awarded a €14 million ERC Synergy grant. €5 million will be used to back groundbreaking research at TU/e, with Bakkers coordinating the international project.</section><section tabindex="-1">“Light-emitting chips is the holy grail of future computing technologies – the realization of these chips could revolutionize computing technologies.”That’s how&nbsp;<a href="https://www.tue.nl/en/research/researchers/erik-bakkers" target="_blank">Erik Bakkers</a> – Full Professor at the Department of Applied Physics and Science Education – views the promise of light-emitting microchips.<h3>SiGe holds the key</h3>To get to the promised land, though, a fundamental property of the materials used to make our microchips needs to change.“We must change how atoms are arranged relative to each other. In technical terms, we need to move away from the natural cubic structure of many materials to one that is based on the hexagonal arrangement of atoms. If we achieve this, the materials will be able to emit light.”This is the central goal of the project ‘Bright Chips’, a collaboration between Bakkers, Professor Floris Zwanenburg from the University of Twente, and Professor Jonathan Finley from the Technical University of Munich. The project has just received significant funding to the tune of €14 million as part of the ERC Synergy grant initiative.The material of choice for the ‘Bright Chips’ project is silicon germanium (SiGe) – an alloy that has been shown in recent years to have the suitable properties to emit light.<h3>Three’s not a crowd</h3>“We want to understand how and why SiGe emits light, both from a classical and quantum physics perspectives,” says Bakkers. “Our project is a truly multidisciplinary project which combines the worlds of materials science, photonics, and electronics. And each member of the ‘Bright Chips’ project team will focus on one of these three topics.”At TU/e, the Bakkers’ team will fabricate a new material system based on hexagonal SiGe. Thereafter, the team at TU Munich led by Jonathan Finley will characterize the new SiGe material, and using the material, they plan to demonstrate single photon emitters and lasers.Finally, at the University of Twente, Floris Zwanenburg’s group will fabricate and measure the performance of electronic devices that incorporate the SiGe light-emitting components.“A major milestone or goal for Bright Chips is to study optically-connected SiGe-spin qubits. These can be quickly changed, upscaled, and they are expected to be long-lived due to the unique properties of the materials we will work with,” says Bakkers. “We’re excited to get started with the project!”<h3 id="isPasted">Making blood cells</h3>The second project with TU/e involvement to get an ERC Synergy grant is ‘MakingBlood’.&nbsp;<a href="https://www.tue.nl/en/research/researchers/cecilia-sahlgren" target="_blank">Cecilia Sahlgren</a>, a part-time Full Professor at the Department of Biomedical Engineering and mainly based at Åbo Akademi University in Finland, is one of the four principal investigators on the project.“MakingBlood is seeking to make human blood stem cells (also known as hematopoietic stem cells) using human pluripotent stem cells,” says Sahlgren. “At present, blood stem cells are collected from donors.”“However, too often, a suitable stem cell donor cannot be found. We will explore the cellular, molecular, and physical features that are important for the generation of blood stem cells. Lessons learned here will be used to make blood cells in the lab using a dedicated&nbsp;in vitro setup.”TU/e will play two roles in the project. First, researchers will manufacture a high throughput approach to control flow with magnetic cilia, which will be used to build the embryonic niches that are important for the formation of blood stem cells in the human embryo.This will be done in collaboration with&nbsp;<a href="https://research.tue.nl/en/persons/ye-wang" target="_blank" rel="noreferrer">Ye Wang</a>, who is based in the group of Jaap den Toonder at the Department of Mechanical Engineering.Second, researchers will create&nbsp;in vitro models of the embryonic niches where blood stem cells are formed in the embryo. The ‘MakingBlood’ project is coordinated by the Hospital del Mar Research Institute in Barcelona, Spain, by Professor Anna Bigas.The other principal investigators are Gerald de Haan, Research Director of Sanquin, the Dutch Blood Bank, and Dr Cristina Pina, Senior Lecturer in Biomedical Sciences at Brunel University.<hr><h3 id="isPasted">About the ERC Synergy Grant</h3>A group of two to a maximum of four Principal Investigators (PIs) working together and bringing different skills and resources to tackle ambitious research problems. &nbsp;One will be designated as the corresponding PI (cPI).No specific eligibility criteria regarding the academic training&nbsp;are foreseen for ERC Synergy Grants.PI’s must present a competitive track record that is appropriate to their career stage. Proposals are evaluated on the sole criterion of scientific excellence , which takes on the additional meaning of outstanding intrinsic synergetic effect.</section>

Nemea computer chip with light coming out of it. Image: Created by Jason Jung using Midjourney v4

The first project is developing light-based chips to bridge the gap between photonics and electronics. The second project plans to make blood cells using blood stem cells. The two projects are the first ERC Synergy grants for TU/e.

ERC Synergy grants for cutting-edge light-based chips and for blood cells

Now, researchers have introduced a technique for compressing an LLM’s reams of data, which could increase privacy, save energy and lower costs.The&nbsp;<a href="https://arxiv.org/abs/2405.18886">new algorithm</a>, developed by engineers at Princeton and Stanford Engineering, works by trimming redundancies and reducing the precision of an LLM’s layers of information. This type of leaner LLM could be stored and accessed locally on a device like a phone or laptop and could provide performance nearly as accurate and nuanced as an uncompressed version.“Any time you can reduce the computational complexity, storage and bandwidth requirements of using AI models, you can enable AI on devices and systems that otherwise couldn’t handle such compute- and memory-intensive tasks,” said study coauthor&nbsp;<a href="https://engineering.princeton.edu/faculty/andrea-goldsmith">Andrea Goldsmith</a>, dean of Princeton’s School of Engineering and Applied Science and Arthur LeGrand Doty Professor of&nbsp;<a href="https://ece.princeton.edu/">Electrical and Computer Engineering</a>.“When you use ChatGPT, whatever request you give it goes to the back-end servers of OpenAI, which process all of that data, and that is very expensive,” said coauthor&nbsp;<a href="https://sites.google.com/view/rajarshi-saha">Rajarshi Saha</a>, a Stanford Engineering Ph.D. student. “So, you want to be able to do this LLM inference using consumer GPUs [graphics processing units], and the way to do that is by compressing these LLMs.” Saha’s graduate work is coadvised by Goldsmith and coauthor&nbsp;<a href="https://stanford.edu/~pilanci">Mert Pilanci</a>, an assistant professor at Stanford Engineering.The researchers will present&nbsp;<a href="https://arxiv.org/abs/2405.18886">their new algorithm</a> CALDERA, which stands for Calibration Aware Low precision DEcomposition with low Rank Adaptation, at the Conference on Neural Information Processing Systems (NeurIPS) in December. Saha and colleagues began this compression research not with LLMs themselves, but with the large collections of information that are used to train LLMs and other complex AI models, such as those used for image classification. This technique, a forerunner to the new LLM compression approach, was&nbsp;<a href="https://openreview.net/forum?id=rxsCTtkqA9">published</a> in 2023.Training data sets and AI models are both composed of matrices, or grids of numbers that are used to store data. In the case of LLMs, these are called weight matrices, which are numerical representations of word patterns learned from large swaths of text.“We proposed a generic algorithm for compressing large data sets or large matrices,” said Saha. “And then we realized that nowadays, it’s not just the data sets that are large, but the models being deployed are also getting large. So, we could also use our algorithm to compress these models.”While the team’s algorithm is not the first to compress LLMs, its novelty lies in an innovative combination of two properties, one called “low-precision,” the other “low-rank.” As digital computers store and process information as bits (zeros and ones), “low-precision” representation reduces the number of bits, speeding up storage and processing while improving energy efficiency. On the other hand, “low-rank” refers to reducing redundancies in the LLM weight matrices.“Using both of these properties together, we are able to get much more compression than either of these techniques can achieve individually,” said Saha.The team tested their technique using Llama 2 and Llama 3, open-source large language models released by Meta AI, and found that their method, which used low-rank and low-precision components in tandem with each other, can be used to improve other methods which use just low-precision. The improvement can be up to 5%, which is significant for metrics that measure uncertainty in predicting word sequences.They evaluated the performance of the compressed language models using several sets of benchmark tasks for LLMs. The tasks included determining the logical order of two statements, or answering questions involving physical reasoning, such as how to separate an egg white from a yolk or how to make a cup of tea.“I think it’s encouraging and a bit surprising that we were able to get such good performance in this compression scheme,” said Goldsmith, who moved to Princeton from Stanford Engineering in 2020. “By taking advantage of the weight matrix rather than just using a generic compression algorithm for the bits that are representing the weight matrix, we were able to do much better.”Using an LLM compressed in this way could be suitable for situations that don’t require the highest possible precision. Moreover, the ability to fine-tune compressed LLMs on edge devices like a smartphone or laptop enhances privacy by allowing organizations and individuals to adapt models to their specific needs without sharing sensitive data with third-party providers. This reduces the risk of data breaches or unauthorized access to confidential information during the training process. To enable this, the LLMs must initially be compressed enough to fit on consumer-grade GPUs.Saha also cautioned that running LLMs on a smartphone or laptop could hog the device’s memory for a period of time. “You won’t be happy if you are running an LLM and your phone drains out of charge in an hour,” said Saha. Low-precision computation can help reduce power consumption, he added. “But I wouldn’t say that there’s one single technique that solves all the problems. What we propose in this paper is one technique that is used in combination with techniques proposed in prior works. And I think this combination will enable us to use LLMs on mobile devices more efficiently and get more accurate results.”The paper, “<a href="https://arxiv.org/abs/2405.18886">Compressing Large Language Models using Low Rank and Low Precision Decomposition</a>,” will be presented at the Conference on Neural Information Processing Systems (NeurIPS) in December 2024. In addition to Goldsmith, Saha and Pilanci, coauthors include Stanford Engineering researchers Naomi Sagan and Varun Srivastava. This work was supported in part by the U.S. National Science Foundation, the U.S. Army Research Office, and the Office of Naval Research.

Large language models (LLMs) are increasingly automating tasks like translation, text classification and customer service. But tapping into an LLM’s power typically requires users to send their requests to a centralized server — a process that’s expensive, energy-intensive and often slow.

Leaner large language models could enable efficient local use on phones and laptops

Plasma cleaning is a high-tech surface treatment that uses ionized gas to remove microscopic contaminants, enhancing adhesion and durability in materials. This article explains plasma cleaning’s role across industries, its eco-friendly benefits, and emerging trends in sustainable manufacturing.

Plasma Cleaning: Cutting-Edge Innovations, Core Principles, and Real-World Applications

Mouser Electronics-Fri Jun 30 2023 23:59:59 GMT+0200 (Central European Summer Time)

Mouser Electronics-Mon Jul 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Mouser Electronics-Thu Aug 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Mouser Electronics-Thu Aug 31 2023 23:59:59 GMT+0200 (Central European Summer Time)

Mouser Electronics-Sat Sep 30 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Mouser Electronics-Mon Oct 30 2023 14:34:39 GMT+0200 (Eastern European Standard Time)

Mouser Electronics-Tue Oct 31 2023 23:59:59 GMT+0200 (Eastern European Standard Time)

Murata Electronics Europe-Fri Jun 30 2023 23:59:59 GMT+0200 (Central European Summer Time)

Murata Electronics Europe-Mon Jul 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Murata Electronics Europe-Thu Aug 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Murata Electronics Europe-Thu Aug 31 2023 23:59:59 GMT+0200 (Central European Summer Time)

Murata Electronics Europe-Sat Sep 30 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Digi-Key Electronics-Fri Jun 30 2023 23:59:59 GMT+0200 (Central European Summer Time)

Digi-Key Electronics-Mon Jul 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Digi-Key Electronics-Thu Aug 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Digi-Key Electronics-Thu Aug 31 2023 23:59:59 GMT+0200 (Central European Summer Time)

Digi-Key Electronics-Sat Sep 30 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Renesas Electronics-Fri Jun 30 2023 23:59:59 GMT+0200 (Central European Summer Time)

Renesas Electronics-Mon Jul 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Renesas Electronics-Thu Aug 31 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

Renesas Electronics-Thu Aug 31 2023 23:59:59 GMT+0200 (Central European Summer Time)

Renesas Electronics-Sat Sep 30 2023 23:59:59 GMT+0300 (Eastern European Summer Time)

electronics

electronics

Profiles