The deep neural network models that power today’s most demanding machine-learning applications have grown so large and complex that they are pushing the limits of traditional electronic computing hardware.Photonic hardware, which can perform machine-learning computations with light, offers a faster and more energy-efficient alternative. However, there are some types of neural network computations that a photonic device can’t perform, requiring the use of off-chip electronics or other techniques that hamper speed and efficiency.Building on a decade of research, scientists from MIT and elsewhere have developed a new photonic chip that overcomes these roadblocks. They demonstrated a fully integrated photonic processor that can perform all the key computations of a deep neural network optically on the chip.The optical device was able to complete the key computations for a machine-learning classification task in less than half a nanosecond while achieving more than 92 percent accuracy — performance that is on par with traditional hardware.The chip, composed of interconnected modules that form an optical neural network, is fabricated using commercial foundry processes, which could enable the scaling of the technology and its integration into electronics.In the long run, the photonic processor could lead to faster and more energy-efficient deep learning for computationally demanding applications like lidar, scientific research in astronomy and particle physics, or high-speed telecommunications.“There are a lot of cases where how well the model performs isn’t the only thing that matters, but also how fast you can get an answer. Now that we have an end-to-end system that can run a neural network in optics, at a nanosecond time scale, we can start thinking at a higher level about applications and algorithms,” says Saumil Bandyopadhyay ’17, MEng ’18, PhD ’23, a visiting scientist in the Quantum Photonics and AI Group within the Research Laboratory of Electronics (RLE) and a postdoc at NTT Research, Inc., who is the lead author of a paper on the new chip.Bandyopadhyay is joined on the paper by Alexander Sludds ’18, MEng ’19, PhD ’23; Nicholas Harris PhD ’17; Darius Bunandar PhD ’19; Stefan Krastanov, a former RLE research scientist who is now an assistant professor at the University of Massachusetts at Amherst; Ryan Hamerly, a visiting scientist at RLE and senior scientist at NTT Research; Matthew Streshinsky, a former silicon photonics lead at Nokia who is now co-founder and CEO of Enosemi; Michael Hochberg, president of Periplous, LLC; and Dirk Englund, a professor in the Department of Electrical Engineering and Computer Science, principal investigator of the Quantum Photonics and Artificial Intelligence Group and of RLE, and senior author of the paper. The research&nbsp;<a href="https://www.nature.com/articles/s41566-024-01567-z" target="_blank">appears today in&nbsp;Nature Photonics</a>.<h2>Machine learning with light</h2>Deep neural networks are composed of many interconnected layers of nodes, or neurons, that operate on input data to produce an output. One key operation in a deep neural network involves the use of linear algebra to perform matrix multiplication, which transforms data as it is passed from layer to layer.But in addition to these linear operations, deep neural networks perform nonlinear operations that help the model learn more intricate patterns. Nonlinear operations, like activation functions, give deep neural networks the power to solve complex problems.In 2017, Englund’s group, along with researchers in the lab of Marin Soljačić, the Cecil and Ida Green Professor of Physics,&nbsp;<a href="https://news.mit.edu/2017/new-system-allows-optical-deep-learning-0612" target="_blank">demonstrated an optical neural network on a single photonic chip</a> that could perform matrix multiplication with light.But at the time, the device couldn’t perform nonlinear operations on the chip. Optical data had to be converted into electrical signals and sent to a digital processor to perform nonlinear operations.“Nonlinearity in optics is quite challenging because photons don’t interact with each other very easily. That makes it very power consuming to trigger optical nonlinearities, so it becomes challenging to build a system that can do it in a scalable way,” Bandyopadhyay explains.They overcame that challenge by designing devices called nonlinear optical function units (NOFUs), which combine electronics and optics to implement nonlinear operations on the chip.The researchers built an optical deep neural network on a photonic chip using three layers of devices that perform linear and nonlinear operations.<h2>A fully-integrated network</h2>At the outset, their system encodes the parameters of a deep neural network into light. Then, an array of programmable beamsplitters, which was&nbsp;demonstrated&nbsp;in the 2017 paper, performs matrix multiplication on those inputs.The data then pass to programmable NOFUs, which implement nonlinear functions by siphoning off a small amount of light to photodiodes that convert optical signals to electric current. This process, which eliminates the need for an external amplifier, consumes very little energy.“We stay in the optical domain the whole time, until the end when we want to read out the answer. This enables us to achieve ultra-low latency,” Bandyopadhyay says.Achieving such low latency enabled them to efficiently train a deep neural network on the chip, a process known as in situ&nbsp;training that typically consumes a huge amount of energy in digital hardware.“This is especially useful for systems where you are doing in-domain processing of optical signals, like navigation or telecommunications, but also in systems that you want&nbsp;to learn in real time,” he says.The photonic system achieved more than 96 percent accuracy during training tests and more than 92 percent accuracy during inference, which is comparable to traditional hardware. In addition, the chip performs key computations in less than half a nanosecond. &nbsp; &nbsp;&nbsp;“This work demonstrates that computing — at its essence, the mapping of inputs to outputs — can be compiled onto new architectures of linear and nonlinear physics that enable a fundamentally different scaling law of computation versus effort needed,” says Englund.The entire circuit was fabricated using the same infrastructure and foundry processes that produce CMOS computer chips. This could enable the chip to be manufactured at scale, using tried-and-true techniques that introduce very little error into the fabrication process.Scaling up their device and integrating it with real-world electronics like cameras or telecommunications systems will be a major focus of future work, Bandyopadhyay says. In addition, the researchers want to explore algorithms that can leverage the advantages of optics to train systems faster and with better energy efficiency.

Researchers demonstrated a fully integrated photonic processor that can perform all key computations of a deep neural network optically on the chip, which could enable faster and more energy-efficient deep learning for computationally demanding applications like lidar or high-speed telecommunications. Image: Sampson Wilcox, Research Laboratory of Electronics.

This new device uses light to perform the key operations of a deep neural network on a chip, opening the door to high-speed processors that can learn in real-time.

Photonic processor could enable ultrafast AI computations with extreme energy efficiency

<a href="https://seas.harvard.edu/person/jia-liu">Jia Liu</a>, Assistant Professor of Bioengineering;&nbsp;<a href="https://seas.harvard.edu/person/na-li">Na Li</a>, Winokur Family Professor of Electrical Engineering and Applied Mathematics; and&nbsp;<a href="https://seas.harvard.edu/person/petros-koumoutsakos">Petros Koumoutsakos</a>, Herbert S. Winokur, Jr. Professor of Computing in Science and Engineering at the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS), have been awarded an Emerging Frontiers in Research and Innovation (EFRI) grant from the National Science Foundation. The $2 million grant will support research into developing a bio-symbiotic system that mimics the scalability, adaptability, and efficiency of biological neural networks capable of performing long-term, complex computational tasks.The research is a collaboration between SEAS, the Wyss Institute for Biologically Inspired Engineering at Harvard University, and the University of Texas at Austin.The grant is part of the Emerging Frontiers in Research and Innovation (EFRI): Biocomputing through EnGINeering Organoid Intelligence program, which supports research and development of organoid intelligence systems and biocomputing research.At SEAS, Liu’s group brings together researchers from a range of disciplines to develop advanced bioelectronics that integrate nanoelectronics, soft electronics, genetic and genomic engineering, and machine learning to interface with biological systems. Previously, Liu’s group demonstrated the integration of brain organoids with soft and flexible electronics as cyborg organoids for recording and controlling brain organoid development. With the EFRI grant, Liu and his team will test the cyborg brain organoid’s ability to perform computational tasks, with the goal of inspiring new AI algorithms, enhancing data processing efficiency, and advancing machine learning beyond current capabilities.“Current artificial intelligence and machine learning technologies do not match the adaptability and efficiency of biological systems,” said Liu. “Our goal is to develop a seamlessly integrated biological and electronics system for long-term 3D neural network computing, truly merging nature and machine intelligence together.""NSF's investment will lead to biological computing with superior power and efficiency by harnessing the mechanisms behind complex biological behavior for smart systems," said Susan Margulies, NSF Assistant Director for Engineering. "Advances in biocomputing will open new opportunities for artificial intelligence, biotechnology, and more sustainable computing."

Liu and team receive NSF EFRI grant for biocomputing research

Harnessing scalability, adaptability, and efficiency of biological neural networks through flexible brain-computer interfaces

Fine-tuning large language models adapts pre-trained models to specific tasks or domains using tailored datasets, while Retrieval-Augmented Generation (RAG) combines retrieval systems with generative models to dynamically incorporate external, up-to-date knowledge into outputs.

RAG vs Fine-Tuning: Differences, Benefits, and Use Cases Explained

This article presents a comprehensive technical analysis of CPLD vs FPGA, focusing on their architectural distinctions, performance metrics, design flows, and implementation methodologies. 

CPLD vs FPGA: A Comprehensive Technical Analysis and Implementation Guide

Edge AI Technology Report: Generative AI Edition
Chapter 1. Generative AI's demand for real-time insights is driving a shift from cloud to edge computing, enabling faster, local processing on devices and reducing cloud latency and bandwidth constraints.

Leveraging Edge Computing for Generative AI

<section id="isPasted">Modern computing infrastructures in data centers or distributed computing systems contribute significantly to global electricity use. The increasing demand for electricity in these systems poses problems, as the need for electricity could potentially exceed the world's energy production in the near future.&nbsp;To combat this problem, the&nbsp;<a href="https://new.nsf.gov/news/nsf-awards-42-4m-new-grants-support-future-semiconductors" rel="noopener" target="_blank">National Science Foundation has awarded Future of Semiconductor grants totaling $42.4 million to further research on semiconductors.</a> Part of this effort will be led by Dr. Yuxuan 'Cosmi' Lin, assistant professor in the Department of Materials Science and Engineering at Texas A&amp;M University. His team has received $1.8 million to support a collaborative research project on new designs of interconnect technologies to reduce their power consumption and boost the overall performance of microchips.Microchips contain interconnects — layers of metal conductors with nanoscale to microscale dimensions that connect different electronic devices in a computer chip. About 20-40% of power in microchips is consumed by its interconnects. Copper is the standard material for interconnects due to its abundance, offering low costs and good electrical conductivity. &nbsp;However, when its dimensions are reduced below 10 nanometers, its resistivity increases dramatically, increasing power consumption and heat generation.&nbsp;"First, electrons in ultrathin copper nanowires can no longer move freely due to structure and property changes," said Lin. "Second, the surface of copper nanowires must be encapsulated with an insulating layer to make the structure more stable, but this further reduces charge transport."&nbsp;</section><blockquote>This project offers potential pathways for integrating these new interconnect technologies with silicon integrated circuit chips, paving the way for upscaling such as an emerging industrial development and manufacturing technology.<cite>- Dr. Yuxuan 'Cosmi' Lin</cite></blockquote><section>Throughout this three-year project, the team will develop a new way to synthesize copper nanowires and design effective encapsulation layers based on two-dimensional materials. These break the paradigm, limiting current interconnect technology and enabling next-generation high-performance and energy-efficient computer chips."This project offers potential pathways for integrating these new interconnect technologies with silicon integrated circuit chips, paving the way for upscaling such as an emerging industrial development and manufacturing technology," said Lin.&nbsp;The proposed research, education, and workforce development efforts will be conducted among five interdisciplinary research groups across three universities, including Texas A&amp;M, University of Texas at Austin, and Purdue University. New research initiatives and semiconductor workforce development activities will be coordinated across the three campuses. This will enhance the technological leadership and broader societal impact of Texas A&amp;M in microelectronics, which is one of the critical technologies of national interest as outlined by the CHIPS &amp; Science Act and the Texas CHIPS Act."New domain knowledge will be established at the forefront of the electronic materials area in materials science and engineering throughout this project," said Lin. "Additionally, the project seeks to engage students at all levels, providing training in physics, materials science, and nanoelectronics to prepare students for industry. "&nbsp;Besides Dr. Lin’s group, contributors to the research include the four research groups: Dr. Yuanyue Liu's group and Dr. Jamie Warner's group at UT Austin, as well as Dr. Zhihong Chen's group and Dr. Sumeet Gupta's group at Purdue University.&nbsp;</section>

A research team at Texas A&M has received a $1.8M National Science Foundation Future of Semiconductor grant to develop new energy-efficient interconnect technologies for microchips.

New Energy-efficient Interconnect Technologies for Microchips

The rapid rise of generative AI is pushing the boundaries of computing infrastructure. Traditionally, these AI models have been reliant on cloud-based systems that can meet their need for substantial computational power. However, the demand for real-time, AI-driven decision-making and the need for enhanced privacy and bandwidth efficiency have driven industries to rethink their approach. Enter edge computing: a decentralized computing paradigm that processes data closer to the source, reducing latency and enabling more efficient use of resources. This convergence of generative AI and edge computing transforms industries, enabling personalized, real-time experiences and opening new doors for innovation.<h2 dir="ltr">What’s Driving the Shift to Edge-Based Generative AI?</h2>The push toward deploying generative AI at the edge stems from enabling real-time data processing, enhanced privacy, and personalized experiences across sectors like healthcare, manufacturing, and automotive. The ability to process data on-site rather than in a centralized cloud environment is essential for applications requiring split-second decisions. In the automotive industry, edge-based generative AI enhances autonomous vehicles by generating synthetic data of weather and traffic scenarios in real time to manage diverse driving conditions, allowing vehicles to adapt quickly to obstacles.Privacy and security concerns also play a significant role. Many sectors, especially those handling sensitive data like finance or healthcare, benefit from processing data locally on edge devices. Keeping data close to the source means less risk of exposure during transmission, bolstering data privacy. This trend is amplified as more companies adopt generative AI solutions and become more cautious about how much access they give to cloud-based AI services.Another critical factor is bandwidth and latency reduction. Generative AI applications can be bandwidth-hungry, particularly when reliant on constant cloud connectivity. By shifting part of the data processing to edge devices, organizations can reduce the network load and the latency involved in transmitting data back and forth between devices and the cloud. As AI-driven applications become more widespread, this ability to handle more data locally will be essential for scaling operations.Lastly, personalization is key. Generative AI at the edge allows for dynamic personalization based on real-time data. For example, in the retail sector, AI can analyze customer preferences on the spot and adjust product recommendations accordingly. This edge-driven personalization improves user experience and creates new opportunities for businesses to engage with their customers in more meaningful ways.<h2 dir="ltr">Industry Leaders Driving Edge AI Innovation</h2>Several leading companies are already exploring the potential of combining generative AI with edge computing. NVIDIA’s IGX Orin Developer Kit, for instance, is designed to meet the computational demands of LLMs in industrial and medical environments. This system processes vast amounts of data in real time, making it suitable for AI-powered sensors in these sectors. Another example is Ambarella’s N1 System-on-Chip series, which supports multi-modal LLMs with low power consumption, making it ideal for edge applications like autonomous robots.Moreover, partnerships between semiconductor companies and AI vendors are accelerating the deployment of generative AI at the edge. Qualcomm’s collaboration with Meta to integrate Llama LLMs directly onto edge devices is a prominent example. These strategic alliances are vital in reducing the need for constant cloud connectivity and enabling more localized AI operations.<h2 dir="ltr">Challenges in Harnessing Generative AI at the Edge</h2>Despite the numerous benefits, deploying generative AI at the edge is not without its challenges.&nbsp;<iframe id="66c43956689bde22544360c3" width="250" class="specs-iframe" height="440" src="https://wevolver.com/iframe/specs/microchip-technology-ev58g97a-curiosity-nano-explorer-board?iframe=true" frameborder="0" scrolling="no" data-lf-form-tracking-inspected-kn9eq4roawkarlvp="true" data-lf-yt-playback-inspected-kn9eq4roawkarlvp="true" data-lf-vimeo-playback-inspected-kn9eq4roawkarlvp="true"></iframe> Perhaps the biggest hurdle is the resource-constrained nature of edge devices. While cloud servers can host large, resource-intensive models, edge devices—whether sensors, microcontrollers, or edge servers—often lack the computational power and memory required for such models. To address this, techniques like model pruning, quantization, and knowledge distillation have become useful in optimizing AI models for edge deployment.Model pruning involves simplifying the model by removing non-essential components, thus reducing the computational load. Quantization, on the other hand, lowers the precision of the numbers used in the models, reducing memory usage and processing requirements. Knowledge distillation is a technique in which a smaller “student” model learns from a larger, more complex “teacher” model, retaining much of the performance while optimizing for edge devices.Even with these optimizations, deploying large-scale generative models simultaneously on resource-limited edge servers is challenging. However, innovations in split learning and federated learning provide promising avenues for scaling generative AI across distributed networks of edge devices. In split learning, different parts of a model are run on different devices, while federated learning allows multiple devices to collaborate on training a model without the need to share raw data. These strategies help distribute the computational burden while maintaining model accuracy and performance.<h2 dir="ltr">The Road Ahead</h2>As the convergence of generative AI and edge computing continues to gain momentum, new advancements are on the horizon. Research is increasingly focusing on enabling more complex AI tasks at the edge, with innovations like multi-modal LLMs that simultaneously process text, images, audio, and video. Gartner projects that by 2027, 40% of generative AI solutions will be multimodal, up from just 1% in 2023. This is especially relevant in sectors like telecommunications, where the rollout of 5G and 6G networks will enable more sophisticated AI applications with lower latency.Edge-based generative AI will also be fundamental in enhancing personalization and user experiences, especially as 75% of businesses are expected to use generative AI to create synthetic customer data by 2026. This synthetic data can drive innovation, particularly in regulated industries, by enabling rapid prototyping and creating new, tailored experiences in real time without privacy concerns. By processing data closer to the user, edge AI systems can respond to individual needs and preferences in real time, creating tailored experiences in everything from retail to autonomous driving.The merging of generative AI and edge computing is unlocking new possibilities across industries, driving real-time data processing, enhancing privacy and security, and enabling dynamic personalization. As organizations continue to explore and adopt these technologies, the focus will increasingly shift toward optimizing the deployment of AI at the edge, ensuring that these systems are both efficient and scalable. The next wave of innovation will undoubtedly push the boundaries of what is possible with AI, offering businesses and consumers alike new ways to engage with technology in a more immediate, personalized, and secure manner.Stay tuned for Wevolver's upcoming "Edge AI Technology: The Generative AI Edition" report, launching in November 2024, which will provide deeper insights into these emerging trends and their transformative potential.<hr><h2 dir="ltr" id="isPasted">Author Bio</h2>Samir Jaber is an editor, writer, and industry expert on topics of technology, science, and engineering. He is the editor-in-chief of the Wevolver 2024 State of Edge AI and 2023 Edge AI Technology reports. Samir is the Chief Editor and Founder of Wryters, a content marketing and consulting agency for the tech and engineering industries. He has comprehensive experience working with Fortune 500 companies and industry leaders as a writer, editor, and consultant. He is an online content specialist with an academic background in mechanical engineering, nanotechnology, and scientific research. Samir is also a featured author in 30+ industrial magazines with a focus on AI, IoT, 3D printing, AVs, nanotechnology, materials science, and sustainability. His experience includes award-winning engineering research and patented engineering design in the fields of nanofabrication and microfluidics.

Edge computing: a decentralized computing paradigm that processes data closer to the source, reducing latency and enabling more efficient use of resources.

Generative AI at the Edge: Unlocking Real-Time Innovation

Researchers at the Karlsruhe Institute of Technology (KIT) have shown for the first time in Germany how so-called tin defects in diamonds can be controlled very precisely using microwaves. These defects have special optical and magnetic properties and can be used as qubits: the smallest computing units for quantum computers and quantum communication. The results are an important step towards the development of powerful quantum computers and secure quantum communication networks. The researchers report in the journal Physical Review X (DOI: 10.1103/PhysRevX.14.031036).Quantum computers and quantum communication are considered to be pioneering technologies for much faster and more secure data processing and transmission compared to classical computers. The basic information units in quantum computers are qubits, the quantum mechanical equivalent of bits in conventional data processing.While in classical digital communication, for example, laser pulses in a fiber optic cable transport information from A to B, quantum mechanics uses individual photons, which in principle makes the exchange of information secure against eavesdropping. Optically addressable qubits, i.e. qubits that can be controlled or read out using light, are suitable for storing the information in the photons and processing it in quantum computers. These can store and process the quantum states and absorb and release them in the form of photons.<h2>The key point is the stability of the qubits</h2>One of the biggest challenges in developing qubits is to extend their coherence time, i.e. the time in which they can stably store information. The extent to which efficient and scalable quantum computers can be developed depends crucially on whether it is possible to control qubits and keep them stable in such a way that their properties can be used in practice.Doctoral students Ioannis Karapatzakis and Jeremias Resch at the KIT Institute of Physics investigated how a special diamond defect, the so-called tin vacancy center (SnV), can be precisely controlled. The work was part of the projects "Quantum Repeater.Link (QR.X)" for secure fiber-based quantum communication and SPINNING, which is working towards a spin-photon-based diamond-based quantum computer, funded by the Federal Ministry of Education and Research.&nbsp;"A defect in the lattice structure of the carbon atoms of a diamond occurs when atoms are missing or replaced by other atoms, such as tin," explains Karapatzakis. Such defects can be used as qubits for quantum communication because they have special optical and magnetic properties that allow their states, such as the electron spin, to be specifically manipulated using light or microwaves. This can make the defects usable as stable qubits that can store and process information and couple it to photons.&nbsp;<h2>Coherence times could be significantly improved</h2>The diamond qubits have the advantage of being in solid form. This makes them easier to handle than other quantum materials such as atoms in a vacuum. By controlling them with microwaves, Karapatzakis and Resch managed to precisely influence the electron spins of the tin vacancy center qubits and make this visible. "We were able to significantly improve the coherence times of the SnV centers in diamond to up to ten milliseconds," says Resch. This was achieved using the method of dynamic decoupling, which largely minimizes interference factors. Another special feature is that the two doctoral students were able to show for the first time that this type of diamond defect can be controlled very efficiently using superconducting waveguides: These guide the microwaves efficiently to the defects without generating heat. "This is of great importance because these defects are generally researched at very low temperatures close to absolute zero. Increased temperatures would render the qubits unusable," says Karapatzakis."In order to establish communication between two users or, in the future, two quantum computers, I have to be able to transfer the quantum states of the qubit to photons," explains Resch. "By optically reading out the qubit and achieving stable spectral properties, we were able to take an important step in this direction. Our results on controlling tin vacancy centers in diamonds therefore have the potential for an important breakthrough in the further development of secure and efficient quantum communication."&nbsp;<hr>Original publicationIoannis Karapatzakis, Jeremias Resch, Marcel Schrodin, Philipp Fuchs, Michael Kieschnick, Julia Heupel, Luis Kussi, Christoph Sürgers, Cyril Popov, Jan Meijer, Christoph Becher, Wolfgang Wernsdorfer, David Hunger: Phys. Rev. X 14, 27 August 2024, <a href="https://doi.org/10.1103/PhysRevX.14.031036" target="_blank">DOI: 10.1103/PhysRevX.14.031036</a>

The precise control of diamond qubits is a significant step in the development of quantum computers. (Image: Ioannis Karapatzakis, KIT)

Important breakthrough for the development of diamond-based quantum computers

Quantum Communication: Efficient Microwave Control of Diamond Qubits

This easy-to-understand guide explains how to use timers and counters in PLC programming, with insights on using them to their full potential.<h2 dir="ltr">What Are Timers And Counters?</h2>Timers and counters in PLCs are advanced software-based functions that accurately replicate the operations of traditional hardware, such as&nbsp;<a title="Relays And Timers" href="https://www.rowse-automation.co.uk/control-signalling/relays-timers" target="_blank">relays and timers</a>, along with mechanical counters.These timers and counters allow for the automation of processes based on time delays or event counts, providing more flexibility and reliability. By integrating these functions into PLC programming, complex tasks can be automated, operations streamlined and overall process control enhanced.Timers and counters are often essential for controlling various machines and processes in industrial settings. They can delay the activation of equipment, count the number of items produced, or trigger specific actions after a predetermined time. Their applications are broad, making them invaluable in industries such as manufacturing, automotive production, and material handling.<h2 dir="ltr">Timers</h2>Timers in PLCs function similarly to traditional timing relays but offer significantly enhanced capabilities and greater customisation options. They are primarily used to introduce precise delays or control the timing of various operations within a PLC programme. Timers are assigned specific addresses and come with adjustable settings such as time base, preset value and accumulated value.Some argue that there are as many as&nbsp;<a title="11 Different Types Of PLC Timers" href="https://ladderlogicworld.com/plc-timer/" target="_blank">11 different types of PLC timers</a>. But in most instances, there are two primary timer functions in PLC programming that are important to know about:<h3 dir="ltr">1. Timer On-Delay (TON)</h3>The Timer On-Delay (TON) is one of the most frequently used timer functions in PLC programming. When the logic conditions of the programme rung are met, the TON starts counting based on the specified time interval. The value increases until it reaches the preset value. The associated output is activated at this point and any related contacts within the program are updated. For example, in an automated conveyor system, a TON might delay the conveyor's start when a sensor detects an object, allowing for another process to be completed before the conveyor begins moving.<h3 dir="ltr">2. Timer Off-Delay (TOF)</h3>The Timer Off-Delay (TOF) function is utilised when a delay is required after a signal is deactivated. Unlike the TON, the TOF starts counting when the rung condition becomes false. When the value reaches the preset value, the output is deactivated and the associated contacts revert to their initial state. For example, a TOF might be used in lighting control systems to keep the lights on for a short period of time after a switch is turned off, resulting in a gradual dimming rather than instant turn-off.&nbsp;<h2 dir="ltr">Counters</h2>Counters in PLCs are designed to track specific events, such as the passage of products past a sensor or the completion of machine cycles. Unlike timers, counters do not rely on an internal clock. Instead, they count based on external triggers or program logic. This feature is crucial for applications where precise event tracking is necessary. Counters are usually categorised into one of two types:&nbsp;<h3 dir="ltr">1. Count Up (CTU) &nbsp;</h3>This function increases the counter by one each time the specified event occurs. For example, a CTU could count the number of units passing a quality control sensor. The output is only activated once the accumulated count equals the preset value and the associated contacts change state.<h3 dir="ltr">2. Count Down (CTD)</h3>This function decreases the counter by one each time the event occurs, making it ideal for precise tracking. This is especially useful in various applications where an accurate countdown is necessary, such as monitoring remaining units in a production batch or controlling the sequence of operations.Both CTU and CTD counters are essential in applications requiring accurate counting and control. They are particularly valuable in systems where it’s important to track the progression or depletion of materials or products, ensuring that the process remains within specified limits or targets.<h2 dir="ltr">Resetting Timers And Counters</h2>In some complex industrial processes, it’s often necessary to reset timers and counters to their initial state. This is accomplished using the Reset (RES) instruction, which effectively clears the accumulated value of the associated timer or counter, allowing for the restarting of the counting or timing process.For example, once a production batch is completed in a manufacturing system, the RES instruction can reset the counter, preparing the system for the next batch. The RES instruction must reference the same address as the timer or counter it’s resetting, ensuring precise control and operation. The ability to reset counters and timers is often crucial in maintaining continuity and accuracy in repeated processes, going a long way towards reducing errors that could arise from leftover values.<h2 dir="ltr">Enhancing Automation Efficiency With Timers And Counters</h2>With the ever-increasing demand for more sophisticated automation, the role of timers and counters continues to evolve. They are now pivotal in scenarios requiring high-speed operations, where traditional mechanical methods may falter due to wear and tear. Their ability to be easily reprogrammed also allows for rapid adjustments in production lines, further enhancing their utility in dynamic industrial environments. This adaptability is crucial for businesses looking to stay ahead of the competition and respond quickly to changes in production demands or process requirements.Optimising the use of timers and counters in PLC programming is crucial for maximising the efficiency of industrial automation systems. Businesses may find they can achieve higher levels of productivity through better control over their automation processes while simultaneously reducing costs. By understanding and implementing these powerful software-based tools effectively, it's possible to boost the performance of automated systems while at the same time enhancing overall reliability.Timers and counters are indispensable tools in PLC programming. When used effectively, they can transform automation processes, making them more efficient, reliable, and tailored to your needs.

Programmable Logic Controllers (PLCs) enable precise control over various tasks involved in industrial automation processes. Among the many functionalities that PLCs offer, timers and counters are critical tools for automating tasks, working to enhance automation efficiency and boosting accuracy.

How To Use Timers And Counters In PLC Programming

The rise of Artificial Intelligence (AI) and Machine Learning (ML) has rapidly impacted today's global economy, influencing everything from healthcare to autonomous systems. As of 2023, 55% of organizations used AI in at least one business unit or function, compared to only 20% in 2017 [1].As it permeates more of our economies and daily lives, AI extends beyond the technical. Every country around the world needs to work out their strategy to unlock the potential of AI to solve local problems, while also being able to access the possibilities of a worldwide market. Now, as nations rush to harness the power of AI, it has become clear that the development of robust, performant, and efficient AI/ML computing resources is a global necessity.&nbsp;Enabling widespread access to AI/ML hardware and software is now a matter of global importance. RISC-V is a proven player in this effort. In this article, we’ll explore how RISC-V can transform the AI/ML sector, promote consensus-driven development and global collaboration, and bring socioeconomic benefits to countries around the world.<h1 dir="ltr">Improving Programmer Productivity With a Unified Model</h1>A unique aspect of RISC-V is its unified programming model, which enables the customized development of different types of processors, CPU, GPU and NPU, under a single, consistent set of instructions and interfaces. The model provides programmers with a standardized framework and common tools that enable them to easily write versatile and efficient code across different processing units.&nbsp;Through the use of a single architecture [2], RISC-V eliminates the need for separate programming paradigms for different processing units. As such, RISC-V reduces the learning curve and minimizes the overhead associated with switching between different architectures. Ultimately, this simplifies coding efficiency, reduces errors, and accelerates development cycles.The enhanced productivity facilitated by RISC-V can lead to a competitive edge in technological advancements. Global economies that embrace RISC-V can expedite their custom AI/ML developments to solve local problems and strengthen their positions in the global tech landscape through the adoption of the RISC-V standard. Ideally, this advantage translates into economic growth, job creation, and increased influence in the digital economy.Socioeconomically, RISC-V reduces barriers to entry for AI/ML development and democratizes access to advanced computing capabilities. Such democratization helps to encourage local innovation with worldwide impact across diverse sectors, driving societal progress, and improving quality of life.<h1 dir="ltr">Encouraging International Collaboration</h1>RISC-V is transforming the computing landscape by encouraging unprecedented levels of international collaboration [3].&nbsp;Specifically, the RISC-V industry standard Instruction Set Architecture (ISA) removes proprietary barriers, allowing developers, companies, and academic institutions worldwide to contribute to and benefit from the RISC-V architecture. In contrast to proprietary ISAs, where mainly major players have significant influence, RISC-V allows innovation to emerge from anywhere. It empowers smaller entities and individual contributors to take a first-hand approach in the technological revolution, resulting in a more equitable and dynamic technological ecosystem.The net effect of this openness is the fostering of a global community of innovators, all working cohesively to drive collaborative research and development across borders. By leveraging the collective intelligence and diverse perspectives of an international cohort, RISC-V presents an unprecedented opportunity to accelerate technological advancements in AI. Ultimately, the consensus-driven nature of RISC-V ensures that improvements and innovations are shared broadly.RISC-V is also unique in that, by adhering to a common set of standards, it enables unprecedented ease of integration and interoperability among hardware and software developed by different entities worldwide. As a result, companies, governments, universities and developers can work together more effectively, pooling their resources and expertise to tackle complex challenges collectively and push the state of the industry forward.&nbsp;The implications of this collaborative approach are significant. Nations that embrace RISC-V can enhance their technological capabilities through shared knowledge and resources. Brazil, for example, is developing AI infrastructure based on RISC-V, focused on High-Performance Computing (HPC), semiconductor technology, and large language models [4]. Such a collaborative spirit can lead to stronger international alliances and partnerships and drive economic growth and technological progress on a global scale.&nbsp;<h1 dir="ltr">Breaking Vendor Lock-In</h1>Finally, one of RISC-V’s most important value propositions is that it introduces a new paradigm in which developers and companies have a wider range of choices for AI processing. Namely, the RISC-V ISA enables the design and implementation of custom processors, and also for the RISC-V semiconductor ecosystem to develop a wider range of pre-developed AI chips to choose from. Expertise and technologies from the RISC-V ecosystem of members can support any development, with a breadth of choice that also prevents your choice of AI vendor creating a long term dependency. &nbsp;By eliminating vendor lock-in, RISC-V enables developers to work faster, be more creative, and explore more flexible and rapid development cycles. RISC-V can further support the development and use of advanced technologies without restrictions on innovation. Where the goal is to create an equitable AI/ML landscape, RISC-V can help regions innovate independently, foster local talent, and establish a robust technological infrastructure that supports long-term growth and sustainability, while also maintaining access to a global market and ecosystem of partners.The benefits of breaking vendor lock-in extend significantly to the automotive industry, for example, which is currently undergoing its own set of transformations. Here, RISC-V offers the flexibility needed to innovate and remain competitive on a global scale. As cars become more and more defined by software workloads, including increased use of AI, manufacturers can leverage RISC-V to develop bespoke hardware solutions tailored to the specific needs of their markets [5], ensuring they keep pace with or even surpass their global competitors.&nbsp;Overall, by freeing the industry from vendor lock-in, RISC-V can give developers worldwide, and &nbsp;regions like Europe and Brazil, the tools needed to lead technological innovation and develop true digital sovereignty.&nbsp;<h1 dir="ltr">Conclusion&nbsp;</h1>The modern emergence of AI/ML is more than a simple technical phenomenon; it’s a movement with significant worldwide implications. As nations strive for digital sovereignty, RISC-V offers the tools needed to build robust, independent technological infrastructures while also enabling access to a global market and ecosystem of partner expertise.RISC-V is truly a catalyst for an equitable and collaborative future in AI and ML. As the importance of global deployment of AI/ML continues to grow, RISC-V will undoubtedly have a major role to play in the future of computing around the world.&nbsp;<h1 dir="ltr">References</h1>[1] <a href="https://aiindex.stanford.edu/report/" target="_blank">https://aiindex.stanford.edu/report/</a>[2]&nbsp;<a href="https://riscv.org/technical/specifications/" target="_blank">https://riscv.org/technical/specifications/</a>&nbsp;[3]<a href="https://riscv.org/blog/2023/10/risc-v-an-open-standard-backed-by-a-global-community-to-enable-open-computing-for-all/" target="_blank">https://riscv.org/blog/2023/10/risc-v-an-open-standard-backed-by-a-global-community-to-enable-open-computing-for-all/</a>[4]<a href="https://riscv.org/blog/2024/09/advancing-ai-the-brazilian-way-fostering-innovation-through-collaboration-and-open-standards/" target="_blank">https://riscv.org/blog/2024/09/advancing-ai-the-brazilian-way-fostering-innovation-through-collaboration-and-open-standards/</a>&nbsp;[5]<a href="https://riscv.org/blog/2024/08/infineon-harness-the-power-of-risc-v-for-next-generation-automotive-mcu-innovation/" target="_blank">https://riscv.org/blog/2024/08/infineon-harness-the-power-of-risc-v-for-next-generation-automotive-mcu-innovation/</a>

RISC-V offers the tools needed to foster local AI innovation while also enabling worldwide collaboration and access to a global market 

How RISC-V Changes the Global Landscape of AI and ML

A GPU microchip for accelerated AI processing

Unleashing the Power of GPU, understanding the essential strategies for efficient Deep Learning Model Training without compromising on memory and hardware resources in Graphical Processing Units

Maximize GPU Utilization for Model Training: Unlocking Peak Performance

Phase separation, when molecules part like oil and water, works alongside oxygen diffusion to help memristors—electrical components that store information using electrical resistance—retain information even after the power is shut off, according to a University of Michigan led study recently published in Matter.Up to this point, explanations have not fully grasped how memristors retain information without a power source, known as nonvolatile memory, because models and experiments do not match up.“While experiments have shown devices can retain information for over 10 years, the models used in the community show that information can only be retained for a few hours,” said Jingxian Li, U-M doctoral graduate of materials science and engineering and first author of the study.To better understand the underlying phenomenon driving nonvolatile memristor memory, the researchers focused on a device known as resistive random access memory or RRAM, an alternative to the volatile RAM used in classical computing, and are particularly promising for energy-efficient artificial intelligence applications.&nbsp;The specific RRAM studied, a filament-type valence change memory (VCM), sandwiches an insulating tantalum oxide layer between two platinum electrodes. When a certain voltage is applied to the platinum electrodes, a conductive filament forms a tantalum ion bridge passing through the insulator to the electrodes, which allows electricity to flow, putting the cell in a low resistance state representing a “1” in binary code. If a different voltage is applied, the filament is dissolved as returning oxygen atoms react with the tantalum ions, “rusting” the conductive bridge and returning to a high resistance state, representing a binary code of “0”.&nbsp;It was once thought that RRAM retains information over time because oxygen is too slow to diffuse back. However, a series of experiments revealed that previous models have neglected the role of phase separation.&nbsp;“In these devices, oxygen ions prefer to be away from the filament and will never diffuse back, even after an indefinite period of time. This process is analogous to how a mixture of water and oil will not mix, no matter how much time we wait, because they have lower energy in a de-mixed state,” said&nbsp;<a href="https://mse.engin.umich.edu/people/yiyangli" target="_blank" rel="noreferrer noopener">Yiyang Li</a>, U-M assistant professor of materials science and engineering and senior author of the study.To test retention time, the researchers sped up experiments by increasing the temperature. One hour at 250°C is equivalent to about 100 years at 85°C—the typical temperature of a computer chip.Using the extremely high-resolution imaging of atomic force microscopy, the researchers imaged filaments, which measure only about five nanometers or 20 atoms wide, forming within the one micron wide RRAM device. &nbsp;“We were surprised that we could find the filament in the device. It’s like finding a needle in a haystack,” Li said.&nbsp;The research team found that different sized filaments yielded different retention behavior. Filaments smaller than about 5 nanometers dissolved over time, whereas filaments larger than 5 nanometers strengthened over time. The size-based difference cannot be explained by diffusion alone.Together, experimental results and models incorporating thermodynamic principles showed the formation and stability of conductive filaments depend on phase separation.&nbsp;The research team leveraged phase separation to extend memory retention from one day to well over 10 years in a rad-hard memory chip—a memory device built to withstand radiation exposure for use in space exploration.&nbsp;Other applications include in-memory computing for more energy efficient AI applications or memory devices for electronic skin—a stretchable electronic interface designed to mimic the sensory capabilities of human skin. Also known as e-skin, this material could be used to provide sensory feedback to prosthetic limbs, create new wearable fitness trackers or help robots develop tactile sensing for delicate tasks.“We hope that our findings can inspire new ways to use phase separation to create information storage devices,” Li said.Researchers at Ford Research, Dearborn; Oak Ridge National Laboratory; University at Albany; NY CREATES; Sandia National Laboratories; and Arizona State University, Tempe contributed to this study.The device was built in the&nbsp;<a href="https://lnf.engin.umich.edu/" target="_blank" rel="noreferrer noopener">Lurie Nanofabrication Facility</a> and studied at the&nbsp;<a href="https://mc2.engin.umich.edu/" target="_blank" rel="noreferrer noopener">Michigan Center for Materials Characterization</a>. The work at the University of Michigan was primarily funded by the National Science Foundation (ECCS-2106225).

Newly discovered role of phase separation can help develop memory devices for energy-efficient AI computing.

Solving a memristor mystery to develop efficient, long-lasting memory devices

<h2 id="isPasted"><iframe id="66c33d8585cc0ed55e5ec302" width="250" class="specs-iframe" height="440" src="https://wevolver.com/iframe/specs/renesas-electronics-ra8m1-voice-kit?iframe=true" frameborder="0" scrolling="no" data-lf-form-tracking-inspected-kn9eq4roawkarlvp="true" data-lf-yt-playback-inspected-kn9eq4roawkarlvp="true" data-lf-vimeo-playback-inspected-kn9eq4roawkarlvp="true"></iframe>Enhancing Security Using the Latest Technology</h2>Security is a topic on everyone’s minds today, and as technology gets more advanced, it can be easier to bypass the older systems that others have built. Large-scale system hacks are highly publicized and can affect a wide range of people, but smaller scale hacks can be just as devastating. Therefore, it’s essential to use the best technology to protect what matters most, such as your home and family. Face recognition can provide a more effective home security solution than traditional keys and keypads. Physical keys can be duplicated, stolen, lost, or forgotten, and key codes can be guessed, forgotten, or shared with unauthorized users. Accurate face recognition technology has none of those disadvantages, and owners can easily manage the authorization of each person and log their entries.With some of these legacy security systems becoming easier to bypass, we need to constantly develop new solutions using the latest technology to keep the highest level of security. This is where the smart door lock, utilizing machine learning and 3D facial recognition from AMD technology partner Makarena Labs, comes into play. In this blog, we discuss how smart door technology is bringing peace of mind to the front door and more with a superior level of security.<h2>Addressing Current Security Problems in Smart Door Locks</h2>Smart door locks can provide increased protection for homes and other consumer dwelling spaces, like garages or sheds, but previous versions of smart locks can be easily tricked. Due to the incorporated technology—generally a standard CMOS sensor—previous smart locks can be fooled into opening by using 2D pictures of an authorized person’s face. This results in a false recognition and the system will allow an unauthorized person entry, which is a major security breach that needs to be addressed. &nbsp;AMD, in partnership with Makarena, have developed a capable solution, based on the AMD <a href="https://www.mouser.com/new/xilinx/xilinx-zynq-7000-socs/" target="_blank">Zynq™ 7000 SoC</a>, that provides a fully functional and robust design using 3D facial recognition. This advanced facial recognition is achieved through a camera that uses IR Time-of-Flight (TOF) or Lidar technology to bounce a pattern off the face of the person attempting to gain entry, while the sensors in the smart lock capture the reflection (Figure 1).<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzI1ODUzMjUwMjExLUZpZ3VyZV8xX01ha2FyZW5hX0xhYnNfU21hcnRfTG9jay5wbmciLCJlZGl0cyI6eyJyZXNpemUiOnsid2lkdGgiOjk1MCwiZml0IjoiY292ZXIifX19" style="width: 100%px;" class="fr-fic fr-dib">Figure 1: This smart lock design, developed by AMD and their partner Makarena, is based on the AMD Zynq 7000 SoC, incorporates IR TOF or Lidar technology to detect and create a 3D map of the face, and compares the 3D map to the authorized users in the system, only unlocking if a match is found. (Source: AMD)Using the reflection captured by the sensors, the system creates a 3D map of the face and compares it to the authorized users in the system, only unlocking if a match is found (Figure 2). The CMOS sensor provides an added layer of accuracy and simplifies user management for the homeowner by providing images of each authorized user.<img src="https://images.wevolver.com/eyJidWNrZXQiOiJ3ZXZvbHZlci1wcm9qZWN0LWltYWdlcyIsImtleSI6ImZyb2FsYS8xNzI1ODUzMjcwNDY5LUZpZ3VyZTJfRGV0ZWN0aW9uX2F1dGhvcml6YXRpb25fcHJvY2Vzcy53ZWJwIiwiZWRpdHMiOnsicmVzaXplIjp7IndpZHRoIjo5NTAsImZpdCI6ImNvdmVyIn19fQ==" style="width: 100%px;" class="fr-fic fr-dib">Figure 2: The smart door lock’s detection and authorization process ensures accuracy while simplifying user management. (Source: AMD)This advanced smart door lock system also works in complete darkness and can recognize authorized people even while they are wearing glasses, hats, or facial covers.The AMD Zynq 7000 SoC design can be easily configured and customized by OEMs with help on hand from Makarena Labs, providing a lock that can store a family’s authorized faces and accurately authorize or reject them in under a second. For applications that need to store a larger number of faces, such as a neighborhood’s security gate, the higher performance AMD&nbsp;<a href="https://www.mouser.com/new/xilinx/xilinx-zynq-ultrascale-mpsocs/" target="_blank">Zynq UltraScale+™ MPSoC</a> can support fast recognition even with hundreds of authorized faces. Both parts include robust security engines, which OEM customers can configure to load only authentically signed, encrypted firmware.If you're interested in hearing more about the smart lock solution, please reach out to sales@makarenalabs.com.AMD, and the AMD Arrow logo, UltraScale+, Zynq, and combinations thereof are trademarks of Advanced Micro Devices, Inc.The <a href="https://community.amd.com/t5/adaptive-computing/smart-door-locks-enhancing-security-with-machine-learning/ba-p/583320" rel="noreferrer nofollow" target="_blank">Smart Door Locks – Enhancing Security with Machine Learning</a> blog was first published on amd.com and was reposted here with permission.<hr>Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies, from the endpoint to the edge to the cloud. Specializing in programmable logic devices, Xilinx is the semiconductor company that invented the Field Programmable Gate Array (FPGA), the hardware programmable System on Chip (SoC), and the Adaptive Compute Acceleration Platform (ACAP).

In this blog, we discuss how smart door technology is bringing peace of mind to the front door and more with a superior level of security.

Smart Door Locks - Enhancing Security with Machine Learning

Quantum computers, on the other hand, promise to rapidly crack complex cryptographic systems that a classical computer might never be able to unravel. This promise is based on a quantum factoring algorithm proposed in 1994 by&nbsp;<a href="https://news.mit.edu/2023/weird-weird-quantum-world-peter-shor-killian-lecture-0310" target="_blank">Peter Shor</a>, who is now a professor at MIT.But while researchers have taken great strides in the last 30 years, scientists have yet to build a quantum computer powerful enough to run Shor’s algorithm.As some researchers work to build larger quantum computers, others have been trying to improve Shor’s algorithm so it could run on a smaller quantum circuit. About a year ago, New York University computer scientist Oded Regev proposed a <a href="https://arxiv.org/pdf/2308.06572" target="_blank">major theoretical improvement</a>. His algorithm could run faster, but the circuit would require more memory.Building off those results, MIT researchers have proposed a best-of-both-worlds approach that combines the speed of Regev’s algorithm with the memory-efficiency of Shor’s. This new algorithm is as fast as Regev’s, requires fewer quantum building blocks known as qubits, and has a higher tolerance to quantum noise, which could make it more feasible to implement in practice.In the long run, this new algorithm could inform the development of novel encryption methods that can withstand the code-breaking power of quantum computers.“If large-scale quantum computers ever get built, then factoring is toast and we have to find something else to use for cryptography. But how real is this threat? Can we make quantum factoring practical? Our work could potentially bring us one step closer to a practical implementation,” says Vinod Vaikuntanathan, the Ford Foundation Professor of Engineering, a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL), and senior author of a&nbsp;<a href="https://eprint.iacr.org/2023/1501.pdf" target="_blank" data-lf-fd-inspected-kn9eq4roawkarlvp="true">paper describing the algorithm</a>.The paper’s lead author is Seyoon Ragavan, a graduate student in the MIT Department of Electrical Engineering and Computer Science. The research will be presented at the 2024 International Cryptology Conference.<h2>Cracking cryptography</h2>To securely transmit messages over the internet, service providers like email clients and messaging apps typically rely on RSA, an <a href="https://people.csail.mit.edu/rivest/Rsapaper.pdf" target="_blank" data-lf-fd-inspected-kn9eq4roawkarlvp="true">encryption scheme</a> invented by MIT researchers Ron Rivest, Adi Shamir, and Leonard Adleman in the 1970s (hence the name “RSA”). The system is based on the idea that factoring a 2,048-bit integer (a number with 617 digits) is too hard for a computer to do in a reasonable amount of time.That idea was flipped on its head in 1994 when Shor, then working at Bell Labs, introduced an algorithm which proved that a quantum computer could factor quickly enough to break RSA cryptography.“That was a turning point. But in 1994, nobody knew how to build a large enough quantum computer. And we’re still pretty far from there. Some people wonder if they will ever be built,” says Vaikuntanathan.It is estimated that a quantum computer would need about&nbsp;<a href="https://quantum-journal.org/papers/q-2021-04-15-433/" target="_blank">20 million qubits</a> to run Shor’s algorithm. Right now, the largest quantum computers have around 1,100 qubits.A quantum computer performs computations using quantum circuits, just like a classical computer uses classical circuits. Each quantum circuit is composed of a series of operations known as quantum gates. These quantum gates utilize qubits, which are the smallest building blocks of a quantum computer, to perform calculations.But quantum gates introduce noise, so having fewer gates would improve a machine’s performance. Researchers have been striving to enhance Shor’s algorithm so it could be run on a smaller circuit with fewer quantum gates.That is precisely what Regev did with the circuit he proposed a year ago.“That was big news because it was the first real improvement to Shor’s circuit from 1994,” Vaikuntanathan says.The quantum circuit Shor proposed has a size proportional to the square of the number being factored. That means if one were to factor a 2,048-bit integer, the circuit would need millions of gates.Regev’s circuit requires significantly fewer quantum gates, but it needs many more qubits to provide enough memory. This presents a new problem.“In a sense, some types of qubits are like apples or oranges. If you keep them around, they decay over time. You want to minimize the number of qubits you need to keep around,” explains Vaikuntanathan.He heard Regev speak about his results at a workshop last August. At the end of his talk, Regev posed a question: Could someone improve his circuit so it needs fewer qubits? Vaikuntanathan and Ragavan took up that question.<h2>Quantum ping-pong</h2>To factor a very large number, a quantum circuit would need to run many times, performing operations that involve computing powers, like 2 to the power of 100.But computing such large powers is costly and difficult to perform on a quantum computer, since quantum computers can only perform reversible operations. Squaring a number is not a reversible operation, so each time a number is squared, more quantum memory must be added to compute the next square.The MIT researchers found a clever way to compute exponents using a series of <a href="https://en.wikipedia.org/wiki/Fibonacci_sequence" target="_blank">Fibonacci numbers</a> that requires simple multiplication, which is reversible, rather than squaring. Their method needs just two quantum memory units to compute any exponent.“It is kind of like a ping-pong game, where we start with a number and then bounce back and forth, multiplying between two quantum memory registers,” Vaikuntanathan adds.They also tackled the challenge of error correction. The circuits proposed by Shor and Regev require every quantum operation to be correct for their algorithm to work, Vaikuntanathan says. But error-free quantum gates would be infeasible on a real machine.They overcame this problem using a technique to filter out corrupt results and only process the right ones.The end-result is a circuit that is significantly more memory-efficient. Plus, their error correction technique would make the algorithm more practical to deploy.“The authors resolve the two most important bottlenecks in the earlier quantum factoring algorithm. Although still not immediately practical, their work brings quantum factoring algorithms closer to reality,” adds Regev.In the future, the researchers hope to make their algorithm even more efficient and, someday, use it to test factoring on a real quantum circuit.“The elephant-in-the-room question after this work is: Does it actually bring us closer to breaking RSA cryptography? That is not clear just yet; these improvements currently only kick in when the integers are much larger than 2,048 bits. Can we push this algorithm and make it more feasible than Shor’s even for 2,048-bit integers?” says Ragavan.

The most recent email you sent was likely encrypted using a tried-and-true method that relies on the idea that even the fastest computer would be unable to efficiently break a gigantic number into factors.

Toward a code-breaking quantum computer

With the hype around machine learning (ML) and the rush to transform businesses with it, unsurprisingly, not all ML projects have been a success. Often, a “solution before the problem” mentality leads to poorly defined requirements and goals for the use of ML. Failing to understand why ML should be used, as well as how business metrics will be impacted, may lead to proof of concept (POC) work that takes up valuable time without delivering results. To avoid that, companies seeking to introduce ML into their processes or products should aim to understand their overall goal in doing so and then link that goal to relevant business metrics used to measure a current baseline, setting the stage for assessing ML performance as the POC work progresses. Finally, connecting those indicators to appropriate ML metrics based on the task or use case for the POC and developing a short roadmap for the research and development direction will increase the likelihood of success.<h2>Distilling Goals into Business Metrics</h2>Businesses usually decide to introduce ML into their processes for one of several overarching reasons. Typically, these reasons include improving revenue by increasing the productivity of the team, elevating the success rate of some particular aspect of the business, improving customer outcomes by reducing the time to respond to incoming information, or reducing costs associated with errors or other waste. These reasons tie into more fine-grained business metrics that should be identified when starting an ML project. For example, if the goal is to increase revenue by enhancing the team or company’s capabilities, then relevant metrics for measuring the current state of productivity might relate to sales and marketing metrics such as quota attainment rate, cost per lead, or net sales revenue, among others. For improving customer success, relevant metrics may include churn, customer satisfaction scores, or rate of lost deals. Most importantly, identifying these business needs via correct metrics is crucial when developing projects rather than identifying solutions without understanding the concrete “why” behind their necessity. Deciding to implement an ML process for triaging support tickets or summarizing long documents won’t make sense unless the impact of doing so is effectively measured as a baseline.<h2>Matching Business Metrics to ML Equivalents</h2>Once appropriate business metrics have been chosen for the project based on the overall goals, they should be matched to one or more ML metrics based on the tasks identified for ML to tackle. Typically, a cluster of metrics for the ML side will be needed to capture an improvement on the business side. For example, suppose the goal is to increase productivity by accelerating a team working on a particular process, perhaps quality assurance of software pre-deployment. In that case, the business metrics might be the time from start to end of testing, the number of elements tested, and the number of tests run per session. However, adjacent and equally important metrics include the number of bugs caught pre-deployment and the number of previously passing tests that now fail. When establishing an ML process to handle some of the quality assurance team’s work, the metrics are not just latency or how fast the model can assess expected versus actual output for discrepancies but also model accuracy—specifically, the number of false positives and negatives. Because mistakes that the model makes may need to be assessed by a human, too many flagged issues will add to the team’s workload, and too many missed issues will result in work upstream for the development team. Alongside having a benchmark of the team’s current performance, based on the business metrics discussed, the baseline accuracy is also useful for assessing whether ML performs at least as well to be considered valid.Sometimes, depending on the use case or task and the type of output required, the ML metrics may not be as straightforward as accuracy or error rate. However, some way of measuring how well an ML process is performing usually exists, as long as one can measure how well things work without it. Natural language processing (NLP) is an example of one domain with less direct metrics. For instance, tasks like summarizing text or generating content appear to be difficult to assess on the surface. Still, if some time is spent to build a dataset of input text and examples of the desired output, then metrics such as Recall-Oriented Understudy for Gisting Evaluation (ROUGE) can be used. This and other metrics measure things like the overlap of words between desired and actual output to account for the fact that no single “correct” answer exists; rather, answers vary according to levels of correctness.<h2>Building the ML POC Roadmap</h2>Finally, with the ML metrics defined, the process of building a brief but detailed roadmap of the POC implementation and experimentation approaches can start. This should involve dividing the whole task into smaller, simpler pieces that are quick to validate in terms of success with an ML model, which could include triaging urgent versus non-urgent support tickets instead of a more complicated set of classifications. Additionally, a preliminary literature review or prior art search should be conducted to identify a series of approaches with increasing complexity in case the simpler options fail at the task. Implementing this strategy starts with off-the-shelf models or those available through a third-party application programming interface (if allowable in the business context), then moves to architectures that can be adjusted by fine-tuning or retraining for the particular task, and finishes with those that need to be implemented from scratch with perhaps more complicated training regimes. The costs for each approach can be approximated to provide a fair assessment of the return on investment (ROI) for the ML project based on the expected value. Doing so highlights whether some POC directions will be prohibitively expensive to try and helps set the cutoff point for abandoning the project if the best performance achieved is insufficient.<h2>Conclusion</h2>Introducing ML into a company’s processes or products helps achieve overarching business goals like improving productivity or reducing costs and errors. However, to ensure success, these ML projects need to start on the right foot. Measuring impact via the appropriate business metrics is key, followed by identifying the right ML metrics to show that developed models will provide the expected value because they work as well as required. Once these details are established, building a roadmap to capture the direction of POC implementation will keep the project on track. This roadmap will also ensure that ROI versus effort is tracked so that a sufficient point of abandonment can be identified that balances the two. These best practices are the first of several required to transition from business goals to ML POC to production.Follow this AI blog series to learn the other important stages involved in developing an ML POC in an agile but robust fashion and how to put the resulting outputs into production. Future blogs will cover identifying and establishing a dataset for the project, setting up experimentation tooling, developing resources and approaches for POC-building, including open-source models, creating guidelines and focus points when extending to a production-ready version, as well as considering what to anticipate and monitor post-deployment.

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