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A comprehensive exploration of open circuits, detailing their characteristics, detection methods, and the pivotal role they play in modern engineering systems.

What is an Open Circuit: A Deep Dive for Engineers

The new hardware reimagines AI chips for modern workloads and can run powerful AI systems using much less energy than today’s most advanced semiconductors, according to&nbsp;<a href="https://ece.princeton.edu/people/naveen-verma" target="_blank">Naveen Verma</a>, professor of electrical and computer engineering. Verma, who will lead the project, said the advances break through key barriers that have stymied chips for AI, including size, efficiency and scalability.Chips that require less energy can be deployed to run AI in more dynamic environments, from laptops and phones to hospitals and highways to low-Earth orbit and beyond. The kinds of chips that power today’s most advanced models are too bulky and inefficient to run on small devices, and are primarily constrained to server racks and large data centers.Now, the Defense Advanced Research Projects Agency, or DARPA, has <a href="https://www.linkedin.com/feed/update/urn:li:activity:7162915986004762624/" target="_blank" rel="noopener">announced</a> it will support Verma’s work, based on a suite of key inventions from his lab, with an $18.6 million grant. The DARPA funding will drive an exploration into how fast, compact and power-efficient the new chip can get.“There’s a pretty important limitation with the best AI available just being in the data center,” Verma said. “You unlock it from that and the ways in which we can get value from AI, I think, explode.”The announcement came as part of a broader effort by DARPA to fund “revolutionary advances in science, devices and systems” for the next generation of AI computing. The program, called OPTIMA, includes projects across multiple universities and companies. The program’s call for proposals estimated total funding at $78 million, although DARPA has not disclosed the full list of institutions or the total amount of funding the program has awarded to date.In the Princeton-led project, researchers will collaborate with Verma’s startup,&nbsp;<a href="https://www.enchargeai.com/" target="_blank" rel="noopener">EnCharge AI</a>. Based in Santa Clara, Calif., EnCharge AI is commercializing technologies based on discoveries from Verma’s lab, including several key papers he co-wrote with electrical engineering graduate students going back as far as 2016.Encharge AI “brings leadership in the development and execution of robust and scalable mixed-signal computing architectures,” according to the project proposal. Verma&nbsp;<a href="https://engineering.princeton.edu/news/2023/01/27/encharge-ai-reimagines-computing-meet-needs-cutting-edge-ai" target="_blank">co-founded the company</a> in 2022 with Kailash Gopalakrishnan, a former IBM Fellow, and Echere Iroaga, a leader in semiconductor systems design.Gopalakrishnan said that innovation within existing computing architectures, as well as improvements in silicon technology, began slowing at exactly the time when AI began creating massive new demands for computation power and efficiency. Not even the best graphics processing unit (GPU), used to run today’s AI systems, can mitigate the bottlenecks in memory and computing energy facing the industry.“While GPUs are the best available tool today,” he said, “we concluded that a new type of chip will be needed to unlock the potential of AI.”<h3>The needs are real</h3>Between 2012 and 2022, the amount of computing power required by AI models grew by about 1 million percent, according to Verma, who is also director of the&nbsp;<a href="https://kellercenter.princeton.edu/" target="_blank">Keller Center for Innovation in Engineering Education</a> at Princeton University. To meet demand, the latest chips pack in tens of billions of transistors, each separated by the width of a small virus. And yet the chips still are not dense enough in their computing power for modern needs.Today’s leading models, which combine large language models with computer vision and other approaches to machine learning, were developed using more than&nbsp;<a href="https://cmte.ieee.org/futuredirections/2023/11/14/llms-hitting-2-trillions-parameters/" target="_blank">a trillion variables</a> each. The Nvidia-designed GPUs that have fueled the AI boom have become so valuable, major companies reportedly transport them via armored car. The backlogs to buy or lease these chips stretch to the vanishing point.When Nvidia became only the third company ever to reach a $2 trillion valuation, the Wall Street Journal&nbsp;<a href="https://www.wsj.com/tech/ai/how-a-shifting-ai-chip-market-will-shape-nvidias-future-f0c256b1" target="_blank">reported</a> that a rapidly increasing share of the company’s rising revenue came not through the development of the models, called training, but in chips that enable the use of AI systems once they are already trained. Technologists refer to this deployment stage as inference. And inference is where Verma says his research will have the most impact in the near-to-medium term.“This is all about decentralizing AI, unleashing it from the data center,” he said. “It’s got to move out of the data center into places where we and the processes that matter to us can access computing the most, and that’s phones, laptops, factories, those kinds of things.”<h3>Freeing AI from the cloud</h3>To create chips that can handle modern AI workloads in compact or energy-constrained environments, the researchers had to completely reimagine the physics of computing while designing and packaging hardware that can be manufactured with existing fabrication techniques and that can work well with existing computing technologies, such as a central processing unit.“AI models have exploded in their size,” Verma said, “and that means two things.” AI chips need to become much more efficient at doing math and much more efficient at managing and moving data.Their approach has three key parts.The core architecture of virtually every digital computer has followed a deceptively simple pattern first developed in the 1940s: store data in one place, do computation in another. That means shuttling information between memory cells and the processor. Over the past decade, Verma has pioneered research into an updated approach where the computation is done directly in memory cells, called in-memory computing. That’s part one. The promise is that in-memory computing will reduce the time and energy it costs to move and process large amounts of data.But so far, digital approaches to in-memory computing have been highly limited. Verma and his team turned to an alternate approach: analog computation. That’s part two.“In the special case of in-memory computing, you not only need to do compute efficiently,” Verma said, “you also need to do it with very high density because now it needs to fit inside these very tiny memory cells.” Rather than encoding information in a series of 0s and 1s, and processing that information using traditional logic circuits, analog computers leverage the richer physics of the devices. The curvature of a gear. The ability of a wire to hold electrical charge.Digital signals began replacing analog signals in the 1940s primarily because binary code scaled better with the exponential growth of computing. But digital signals don’t tap deeply into the physics of devices, and as a result they can require more data storage and management. They are less efficient in that way. Analog gets its efficiency from processing finer signals using the intrinsic physics of the devices. But that can come with a tradeoff in precision.“The key is in finding the right physics for the job in a device that can be controlled exceedingly well and manufactured at scale,” Verma said.His team found a way to do highly accurate computation using the analog signal generated by capacitors specially designed to switch on and off with exacting precision. That’s part three. Unlike semiconductor devices such as transistors, the electrical energy moving through capacitors doesn’t depend on variable conditions like temperature and electron mobility in a material.“They only depend on geometry,” Verma said. “They depend on the space between one metal wire and the other metal wire.” And geometry is one thing that today’s most advanced semiconductor manufacturing techniques can control extremely well.

Princeton researchers have totally reimagined the physics of computing to build a chip for modern AI workloads, and with new U.S. government backing they will see how fast, compact and power-efficient this chip can get. An early prototype is pictured above. Photo by Photo by Hongyang Jia/Princeton University

The Defense Department’s largest research organization has partnered with a Princeton-led effort to develop advanced microchips for artificial intelligence.

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Transistors — the tiny on-off switches inside microchips — have gotten smaller and smaller over the years, increasing computing power and enabling smaller devices. During that time, the copper wires that connect these switches have likewise shrunk.However, smaller, thinner wires create a big problem, said Daniel Gall, professor of materials science and engineering at Rensselaer Polytechnic Institute.“The job of the wire is to conduct electrons — electricity. Imagine a wire as a crowded hallway that the electrons have to get through. The narrower the hallway, the more the electrons bump into things and scatter. We call that resistance,” Gall explained.As the wires in chips get smaller and thinner, resistance increases, and efficiency goes down.“Today, resistance is the biggest barrier to more efficient chips,” Gall said.Thanks to a new, three-year&nbsp;<a href="https://new.nsf.gov/news/nsf-partners-invest-45-million-future" target="_blank">$1.2 million grant from the National Science Foundation</a>, Gall will lead collaborators at RPI, Notre Dame University, and Cornell University on a hunt for new materials that can be made even smaller than current copper wires while offering far less electrical resistance.Discovery of such materials may one day lead to smaller, faster, more energy-efficient computer chips, Gall said.The grant will also support a workforce development initiative that will connect hundreds of students and leaders at historically Black colleges and universities, minority-serving institutions, and community colleges; semiconductor experts at research intensive universities; and microelectronics engineers from chip manufacturing companies.This component of the project will advance semiconductor curriculum, generate immersive industry-led courses, establish a seminar series and, at RPI, launch an interdisciplinary master’s degree program in semiconductors technology.“Right now, the semiconductor industry does not reflect the diversity of the U.S. population. To change that, we need to start in the classrooms of institutions that serve those underrepresented in the semiconductor workforce. We are excited to work with researchers and leaders from 21 historically Black colleges and universities and minority-serving institutions to co-design interactive teaching approaches that foster an immersive learning environment and student mentorship,” said Shayla Sawyer, professor of electrical, computer, and systems engineering, who will lead the workforce development component of the project. Sawyer directs the Mercer XLab at Rensselaer, which supports innovative learn-by-doing approaches for students.“No one person or institution alone will be able to effect the changes needed to support a thriving domestic chip industry, which is why RPI is proud to bring together researchers, educators, and students who represent the future of semiconductors in the U.S.,” said Shekhar Garde, dean of Rensselaer’s School of Engineering.<a href="https://new.nsf.gov/funding/opportunities/national-science-foundation-future-semiconductors" target="_blank">The project is funded by NSF’s Future of Semiconductors Program</a>, a public-private partnership aimed at accelerating new chip technologies and developing the U.S. chip manufacturing workforce. This program is made possible by the 2022 CHIPS and Science act.

Transistors — the tiny on-off switches inside microchips — have gotten smaller and smaller over the years, increasing computing power and enabling smaller devices. During that time, the copper wires that connect these switches have likewise shrunk.

With New Grant, RPI Works To Shrink Microchips, Expand Semiconductor Workforce

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Printed Circuit Board with Surface Mounted Devices

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Types of SMD Components: A Comprehensive Guide

In this article, we will delve into the structure and operation of NMOS and PMOS transistors, and discuss the applications and characteristics of these essential components in electronic circuits. 

NMOS and PMOS Transistors: Fundamentals and Applications

This article was first published on <a href="https://news.mit.edu/2023/mit-engineers-2d-materials-computer-chips-0427" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>. &nbsp;&nbsp;<hr>Emerging AI applications, like chatbots that generate natural human language, demand denser, more powerful computer chips. But semiconductor chips are traditionally made with bulk materials, which are boxy 3D structures, so stacking multiple layers of transistors to create denser integrations is very difficult.However, semiconductor transistors made from ultrathin 2D materials, each only about three atoms in thickness, could be stacked up to create more powerful chips. To this end, MIT researchers have now demonstrated a novel technology that can effectively and efficiently &ldquo;grow&rdquo; layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip to enable denser integrations.Growing 2D materials directly onto a silicon CMOS wafer has posed a major challenge because the process usually requires temperatures of about 600 degrees Celsius, while silicon transistors and circuits could break down when heated above 400 degrees. Now, the interdisciplinary team of MIT researchers has developed a low-temperature growth process that does not damage the chip. The technology allows 2D semiconductor transistors to be directly integrated on top of standard silicon circuits.In the past, researchers have grown 2D materials elsewhere and then transferred them onto a chip or a wafer. This often causes imperfections that hamper the performance of the final devices and circuits. Also, transferring the material smoothly becomes extremely difficult at wafer-scale. By contrast, this new process grows a smooth, highly uniform layer across an entire 8-inch wafer.The new technology is also able to significantly reduce the time it takes to grow these materials. While previous approaches required more than a day to grow a single layer of 2D materials, the new approach can grow a uniform layer of TMD material in less than an hour over entire 8-inch wafers.Due to its rapid speed and high uniformity, the new technology enabled the researchers to successfully integrate a 2D material layer onto much larger surfaces than has been previously demonstrated. This makes their method better-suited for use in commercial applications, where wafers that are 8 inches or larger are key.&ldquo;Using 2D materials is a powerful way to increase the density of an integrated circuit. What we are doing is like constructing a multistory building. If you have only one floor, which is the conventional case, it won&rsquo;t hold many people. But with more floors, the building will hold more people that can enable amazing new things. Thanks to the heterogenous integration we are working on, we have silicon as the first floor and then we can have many floors of 2D materials directly integrated on top,&rdquo; says Jiadi Zhu, an electrical engineering and computer science graduate student and co-lead author of a&nbsp;<a href="https://www.nature.com/articles/s41565-023-01375-6" target="_blank">paper</a> on this new technique.Zhu wrote the paper with co-lead-author Ji-Hoon Park, an MIT postdoc; corresponding authors Jing Kong, professor of electrical engineering and computer science (EECS) and a member of the Research Laboratory for Electronics; and Tom&aacute;s Palacios, professor of EECS and director of the Microsystems Technology Laboratories (MTL); as well as others at MIT, MIT Lincoln Laboratory, Oak Ridge National Laboratory, and Ericsson Research. The paper appears today in&nbsp;Nature Nanotechnology.<h2>Slim materials with vast potential</h2>The 2D material the researchers focused on, molybdenum disulfide, is flexible, transparent, and exhibits powerful electronic and photonic properties that make it ideal for a semiconductor transistor. It is composed of a one-atom layer of molybdenum sandwiched between two atoms of sulfide.Growing thin films of molybdenum disulfide on a surface with good uniformity is often accomplished through a process known as&nbsp;<a href="https://news.mit.edu/2015/explained-chemical-vapor-deposition-0619" target="_blank">metal-organic chemical vapor deposition</a> (MOCVD). Molybdenum hexacarbonyl and diethylene sulfur, two organic chemical compounds that contain molybdenum and sulfur atoms, vaporize and are heated inside the reaction chamber, where they &ldquo;decompose&rdquo; into smaller molecules. Then they link up through chemical reactions to form chains of molybdenum disulfide on a surface.But decomposing these molybdenum and sulfur compounds, which are known as precursors, requires temperatures above 550 degrees Celsius, while silicon circuits start to degrade when temperatures surpass 400 degrees.So, the researchers started by thinking outside the box &mdash; they designed and built an entirely new furnace for the metal-organic chemical vapor deposition process.The oven consists of two chambers, a low-temperature region in the front, where the silicon wafer is placed, and a high-temperature region in the back. Vaporized molybdenum and sulfur precursors are pumped into the furnace. The molybdenum stays in the low-temperature region, where the temperature is kept below 400 degrees Celsius &mdash; hot enough to decompose the molybdenum precursor but not so hot that it damages the silicon chip.The sulfur precursor flows through into the high-temperature region, where it decomposes. Then it flows back into the low-temperature region, where the chemical reaction to grow molybdenum disulfide on the surface of the wafer occurs.&ldquo;You can think about decomposition like making black pepper &mdash; you have a whole peppercorn and you grind it into a powder form. So, we smash and grind the pepper in the high-temperature region, then the powder flows back into the low-temperature region,&rdquo; Zhu explains.<h2>Faster growth and better uniformity</h2>One problem with this process is that silicon circuits typically have aluminum or copper as a top layer so the chip can be connected to a package or carrier before it is mounted onto a printed circuit board. But sulfur causes these metals to sulfurize, the same way some metals rust when exposed to oxygen, which destroys their conductivity. The researchers prevented sulfurization by first depositing a very thin layer of passivation material on top of the chip. Then later they could open the passivation layer to make connections.They also placed the silicon wafer into the low-temperature region of the furnace vertically, rather than horizontally. By placing it vertically, neither end is too close to the high-temperature region, so no part of the wafer is damaged by the heat. Plus, the molybdenum and sulfur gas molecules swirl around as they bump into the vertical chip, rather than flowing over a horizontal surface. This circulation effect improves the growth of molybdenum disulfide and leads to better material uniformity.In addition to yielding a more uniform layer, their method was also much faster than other MOCVD processes. They could grow a layer in less than an hour, while typically the MOCVD growth process takes at least an entire day.Using the state-of-the-art&nbsp;<a href="https://mitnano.mit.edu/" target="_blank">MIT.Nano</a> facilities, they were able to demonstrate high material uniformity and quality across an 8-inch silicon wafer, which is especially important for industrial applications where bigger wafers are needed.&ldquo;By shortening the growth time, the process is much more efficient and could be more easily integrated into industrial fabrications. Plus, this is a silicon-compatible low-temperature process, which can be useful to push 2D materials further into the semiconductor industry,&rdquo; Zhu says.In the future, the researchers want to fine-tune their technique and use it to grow many stacked layers of 2D transistors. In addition, they want to explore the use of the low-temperature growth process for flexible surfaces, like polymers, textiles, or even papers. This could enable the integration of semiconductors onto everyday objects like clothing or notebooks.&ldquo;This work made an important progress in the synthesis technology of monolayer molybdenum disulfide material,&rdquo; says Han Wang, the Robert G. and Mary G. Lane Endowed Early Career Chair and Associate Professor of Electrical and Computer Engineering and Chemical Engineering and Materials Science at the University of Southern California, who was not involved with this research. &ldquo;The new capability of low thermal budget growth on an 8-inch scale enables the back-end-of-line integration of this material with silicon CMOS technology and paves the way for its future electronics application.&rdquo;This work is partially funded by the MIT Institute for Soldier Nanotechnologies, the National Science Foundation Center for Integrated Quantum Materials, Ericsson, MITRE, the U.S. Army Research Office, and the U.S. Department of Energy. The project also benefitted from the support of TSMC University Shuttle.<hr>&quot;Reprinted with permission of&nbsp;<a href="https://news.mit.edu/2023/mit-engineers-2d-materials-computer-chips-0427" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>&quot; &nbsp;

Graduate student Jiadi Zhu holding an 8-inch CMOS wafer with molybdenum disulfide thin film. On the right is the furnace the researchers developed, which enabled them to "grow" a layer of molybdenum disulfide onto the wafer using a low-temperature process that did not damage the wafer. Image: Courtesy of the researchers

A new low-temperature growth and fabrication technology allows the integration of 2D materials directly onto a silicon circuit, which could lead to denser and more powerful chips.

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Verilog, a Hardware Description Language (HDL) used to model electronic systems.

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Until now, the ability to make electronic devices faster has come down to a simple principle: scaling down transistors and other components. But this approach is reaching its limit, as the benefits of shrinking are counterbalanced by detrimental effects like resistance and decreased output power.Elison Matioli of the Power and Wide-band-gap Electronics Research Lab (<a href="https://www.epfl.ch/labs/powerlab/" target="_blank">POWERlab</a>) in EPFL&rsquo;s School of Engineering explains that further miniaturization is therefore not a viable solution to better electronics performance. &ldquo;New papers come out describing smaller and smaller devices, but in the case of materials made from gallium nitride, the best devices in terms of frequency were already published a few years back,&rdquo; he says. &ldquo;After that, there is really nothing better, because as device size is reduced, we face fundamental limitations. This is true regardless of the material used.&rdquo;In response to this challenge, Matioli and PhD student Mohammad Samizadeh Nikoo came up with a new approach to electronics that could overcome these limitations and enable a new class of terahertz devices. Instead of shrinking their device, they rearranged it, notably by etching patterned contacts called metastructures at sub-wavelength distances onto a semiconductor made of gallium nitride and indium gallium nitride. These metastructures allow the electrical fields inside the device to be controlled, yielding extraordinary properties that do not occur in nature.Crucially, the device can operate at electromagnetic frequencies in the terahertz range (between 0.3-30 THz) &ndash; significantly faster than the gigahertz waves used in today&rsquo;s electronics. They can therefore carry much greater quantities of information for a given signal or period, giving them great potential for applications in 6G communications and beyond.&ldquo;We found that manipulating radiofrequency fields at microscopic scales can significantly boost the performance of electronic devices, without relying on aggressive downscaling,&rdquo; explains Samizadeh Nikoo, who is the first author of an article on the breakthrough recently&nbsp;<a href="https://www.nature.com/articles/s41586-022-05595-z" rel="noopener" target="_blank">published</a> in the journal&nbsp;Nature.<h2>Record high frequencies, record low resistance</h2>Because terahertz frequencies are too fast for current electronics to manage, and too slow for optics applications, this range is often referred to as the &lsquo;terahertz gap&rsquo;. Using sub-wavelength metastructures to modulate terahertz waves is a technique that comes from the world of optics. But the POWERlab&rsquo;s method allows for an unprecedented degree of electronic control, unlike the optics approach of shining an external beam of light onto an existing pattern.&ldquo;In our electronics-based approach, the ability to control induced radiofrequencies comes from the combination of the sub-wavelength patterned contacts, plus the control of the electronic channel with applied voltage. This means that we can change the collective effect inside the metadevice by inducing electrons (or not),&rdquo; says Matioli.While the most advanced devices on the market today can achieve frequencies of up to 2 THz, the POWERlab&rsquo;s metadevices can reach 20 THz. Similarly, today&rsquo;s devices operating near the terahertz range tend to break down at voltages below 2 volts, while the metadevices can support over 20 volts. This enables the transmission and modulation of terahertz signals with much greater power and frequency than is currently possible.<h2>Integrated solutions</h2>As Samizadeh Nikoo explains, modulating terahertz waves is crucial for the future of telecommunications, as the increasing data requirements of technologies like autonomous vehicles and 6G mobile communications are fast reaching the limits of today&rsquo;s devices. The electronic metadevices developed in the POWERlab could form the basis for integrated terahertz electronics by producing compact, high-frequency chips that can already be used with smartphones, for example.&ldquo;This new technology could change the future of ultra-high-speed communications, as it is compatible with existing processes in semiconductor manufacturing. We have demonstrated data transmission of up to 100 gigabits per second at terahertz frequencies, which is already 10 times higher than what we have today with 5G,&rdquo; Samizadeh Nikoo says. To fully realize the potential of the approach, Matioli says the next step is to develop other electronics components ready for integration into terahertz circuits.&ldquo;Integrated terahertz electronics are the next frontier for a connected future. But our electronic metadevices are just one component. We need to develop other integrated terahertz components to fully realize the potential of this technology. That is our vision and goal.&rdquo;<hr>ReferencesSamizadeh Nikoo, M., Matioli, E. Electronic metadevices for terahertz applications. Nature 614, 451&ndash;455 (2023).&nbsp;<a href="https://www.nature.com/articles/s41586-022-05595-z" rel="noopener" target="_blank">https://doi.org/10.1038/s41586-022-05595-z</a>

EPFL researchers have come up with a new approach to electronics that involves engineering metastructures at the sub-wavelength scale. It could launch the next generation of ultra-fast devices for exchanging massive amounts of data, with applications in 6G communications and beyond.

Electronic metadevices break barriers to ultra-fast communications

This article was first published on&nbsp;<a href="https://news.mit.edu/2023/2d-atom-thin-industrial-silicon-wafers-0118" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>. &nbsp;<hr>True to Moore&rsquo;s Law, the number of transistors on a microchip has doubled every year since the 1960s. But this trajectory is predicted to soon plateau because silicon &mdash; the backbone of modern transistors &mdash; loses its electrical properties once devices made from this material dip below a certain size.Enter 2D materials &mdash; delicate, two-dimensional sheets of perfect crystals that are as thin as a single atom. At the scale of nanometers, 2D materials can conduct electrons far more efficiently than silicon. The search for next-generation transistor materials therefore has focused on 2D materials as potential successors to silicon.But before the electronics industry can transition to 2D materials, scientists have to first find a way to engineer the materials on industry-standard silicon wafers while preserving their perfect crystalline form. And MIT engineers may now have a solution.The team has developed a method that could enable chip manufacturers to fabricate ever-smaller transistors from 2D materials by growing them on existing wafers of silicon and other materials. The new method is a form of &ldquo;nonepitaxial, single-crystalline growth,&rdquo; which the team used for the first time to grow pure, defect-free 2D materials onto industrial silicon wafers.With their method, the team fabricated a simple functional transistor from a type of 2D materials called transition-metal dichalcogenides, or TMDs, which are known to conduct electricity better than silicon at nanometer scales.&ldquo;We expect our technology could enable the development of 2D semiconductor-based, high-performance, next-generation electronic devices,&rdquo; says Jeehwan Kim, associate professor of mechanical engineering at MIT. &ldquo;We&rsquo;ve unlocked a way to catch up to Moore&rsquo;s Law using 2D materials.&rdquo;Kim and his colleagues detail their method in a&nbsp;<a href="https://www.nature.com/articles/s41586-022-05524-0" target="_blank">paper</a> appearing today in&nbsp;Nature. The study&rsquo;s MIT co-authors include Ki Seok Kim, Doyoon Lee, Celesta Chang, Seunghwan Seo, Hyunseok Kim, Jiho Shin, Sangho Lee, Jun Min Suh, and Bo-In Park, along with collaborators at the University of Texas at Dallas, the University of California at Riverside, Washington University in Saint Louis, and institutions across South Korea.<h2>A crystal patchwork</h2>To produce a 2D material, researchers have typically employed a manual process by which an atom-thin flake is carefully exfoliated from a bulk material, like peeling away the layers of an onion.But most bulk materials are polycrystalline, containing multiple crystals that grow in random orientations. Where one crystal meets another, the &ldquo;grain boundary&rdquo; acts as an electric barrier. Any electrons flowing through one crystal suddenly stop when met with a crystal of a different orientation, damping a material&rsquo;s conductivity. Even after exfoliating a 2D flake, researchers must then search the flake for &ldquo;single-crystalline&rdquo; regions &mdash; a tedious and time-intensive process that is difficult to apply at industrial scales.Recently, researchers have found other ways to fabricate 2D materials, by growing them on wafers of sapphire &mdash; a material with a hexagonal pattern of atoms which encourages 2D materials to assemble in the same, single-crystalline orientation.&ldquo;But nobody uses sapphire in the memory or logic industry,&rdquo; Kim says. &ldquo;All the infrastructure is based on silicon. For semiconductor processing, you need to use silicon wafers.&rdquo;However, wafers of silicon lack sapphire&rsquo;s hexagonal supporting scaffold. When researchers attempt to grow 2D materials on silicon, the result is a random patchwork of crystals that merge haphazardly, forming numerous grain boundaries that stymie conductivity.&nbsp;&ldquo;It&rsquo;s considered almost impossible to grow single-crystalline 2D materials on silicon,&rdquo; Kim says. &ldquo;Now we show you can. And our trick is to prevent the formation of grain boundaries.&rdquo;<h2>Seed pockets</h2>The team&rsquo;s new &ldquo;nonepitaxial, single-crystalline growth&rdquo; does not require peeling and searching flakes of 2D material. Instead, the researchers use conventional vapor deposition methods to pump atoms across a silicon wafer. The atoms eventually settle on the wafer and nucleate, growing into two-dimensional crystal orientations. If left alone, each &ldquo;nucleus,&rdquo; or seed of a crystal, would grow in random orientations across the silicon wafer. But Kim and his colleagues found a way to align each growing crystal to create single-crystalline regions across the entire wafer.To do so, they first covered a silicon wafer in a &ldquo;mask&rdquo; &mdash; a coating of silicon dioxide that they patterned into tiny pockets, each designed to trap a crystal seed. Across the masked wafer, they then flowed a gas of atoms that settled into each pocket to form a 2D material &mdash; in this case, a TMD. The mask&rsquo;s pockets corralled the atoms and encouraged them to assemble on the silicon wafer in the same, single-crystalline orientation.&ldquo;That is a very shocking result,&rdquo; Kim says &ldquo;You have single-crystalline growth everywhere, even if there is no epitaxial relation between the 2D material and silicon wafer.&rdquo;With their masking method, the team fabricated a simple TMD transistor and showed that its electrical performance was just as good as a pure flake of the same material.They also applied the method to engineer a multilayered device. After covering a silicon wafer with a patterned mask, they grew one type of 2D material to fill half of each square, then grew a second type of 2D material over the first layer to fill the rest of the squares. The result was an ultrathin, single-crystalline bilayer structure within each square. Kim says that going forward, multiple 2D materials could be grown and stacked together in this way to make ultrathin, flexible, and multifunctional films.&ldquo;Until now, there has been no way of making 2D materials in single-crystalline form on silicon wafers, thus the whole community has almost given up on pursuing 2D materials for next-generation processors,&rdquo; Kim says. &ldquo;Now we have completely solved this problem, with a way to make devices smaller than a few nanometers. This will change the paradigm of Moore&rsquo;s Law.&rdquo;This research was supported in part by the U.S. Defense Advanced Research Projects Agency, Intel, the IARPA MicroE4AI program, MicroLink Devices, Inc., ROHM Co., and Samsung.<hr>&quot;Reprinted with permission of&nbsp;<a href="https://news.mit.edu/2023/2d-atom-thin-industrial-silicon-wafers-0118" id="isPasted" rel="noopener noreferrer" target="_blank">MIT News</a>&quot; &nbsp;

By depositing atoms on a wafer coated in a “mask” (top left), MIT engineers can corral the atoms in the mask’s individual pockets (center middle), and encourage the atoms to grow into perfect, 2D, single-crystalline layers (bottom right). Courtesy of the researchers. Edited by MIT News.

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Diagnosing and monitoring diseases often rely on the detection of molecules called &ldquo;biomarkers&rdquo;. However, the detection of such biomarkers need periodic blood draws, which are expensive, time consuming, require specialised equipment, and provide no continuous data. To avoid this, and provide real-time biomarker detection, Professor Kevin Plaxco&rsquo;s team at the University of California Santa Barbara pioneered the development of implantable aptamer-based sensors. These devices are electrochemical sensors based on DNA and they successfully track small molecules in real time.A key step to translate these sensors to real-life applications in the clinic is to make them as small and minimally invasive as possible. To solve this miniaturisation challenge, researchers at Cambridge1 teamed up with the Plaxco Lab to discover a way to combine aptamer-based sensors with an amplifying transistor platform. Together, they developed biosensors based on organic electrochemical transistors (OECTs), which maintain high performances of the aptamer sensors even when shrunk to quite small dimensions. The <a href="https://doi.org/10.1126/sciadv.add4111" target="_blank">results</a> are reported in the journal Science Advances.Research student <a href="http://www.eng.cam.ac.uk/profiles/sb2410" target="_blank">Sophia Bidinger</a>, lead author of the paper, said: &ldquo;This work is an important step towards creating better tools for healthcare providers. With this type of sensor, physicians will be able to gain unprecedented real-time data for tracking their patients&rsquo; health.&rdquo;&nbsp;Previous aptamer sensors were made of thin, millimeters-long wires. In contrast, the new transistor biosensors are so small that they are barely visible to the naked eye. This technology will be useful for medical applications that require sensors in delicate areas. For example, such a minimally invasive sensor could enable implantation in the brain &ndash; an ideal region to track biomarkers linked with mental disorders, such as depression.&nbsp;Paper co-author <a href="http://www.eng.cam.ac.uk/profiles/th270" target="_blank">Professor Tawfique Hasan</a> said: &ldquo;There is a huge market opportunity for continuous molecular monitoring. Besides glucose, there are not very many commercially available sensors. More tools for supporting continuous, in vivo sensing will save lives.&rdquo;The cross-disciplinary research team will now explore possible next directions of this work. For example, another benefit of signal amplification is improved lifetime, so the sensor can operate for longer without being replaced. Each of these improvements is one step closer to deployment in humans for tracking anything from drugs to hormones to neurotransmitters.&nbsp;Paper co-author <a href="http://www.eng.cam.ac.uk/profiles/gm603" target="_blank">Professor George Malliaras</a> added: &ldquo;The most exciting aspect of this work is that it could be used to detect virtually any small molecule. This will help doctors gain much more patient specific insight than ever before.&rdquo;&nbsp;<hr>Reference: Sophia L. Bidinger; Scott T. Keene; Sanggil Han; Kevin W. Plaxco; George G. Malliaras; Tawfique Hasan. &lsquo;<a href="https://doi.org/10.1126/science.add8544" target="_blank">Pulsed transistor operation enables miniaturization of electrochemical aptamer-based sensors</a>.&rsquo; Science Advances (2022). DOI: 10.1126/sciadv.add41111&nbsp;From the Electrical Engineering Division, Department of Engineering, and the Department of Physics.

Scalable thin film transistor-based biosensors.  Credit: Ben Woodington

A new method for the miniaturisation of biosensors will enable new possibilities for minimally invasive implants. The miniaturised transistors are fabricated on thin, flexible substrates, and amplify biosignals, producing currents more than 200 times larger than analogous alternatives.

Miniaturised biosensors for minimally invasive implants

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